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update project template

Merged update project template
update-project-template into master
Merged Martin Christoph Hierholzer requested to merge update-project-template into master
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include/SamplingScheme.h
+ 29
− 47
@@ -6,8 +6,6 @@
namespace ctk = ChimeraTK;
/**********************************************************************************************************************/
// Define the sampling scheme module dealing with raw mode and daq decimation
struct SamplingScheme : public ctk::ApplicationModule {
using ctk::ApplicationModule::ApplicationModule;
@@ -21,8 +19,19 @@ struct SamplingScheme : public ctk::ApplicationModule {
struct Configuration : ctk::VariableGroup {
using ctk::VariableGroup::VariableGroup;
ctk::ScalarPushInput<double> samplingFrequency{this, "samplingFrequency", "MHz",
"IQ sampling frequency as used for the ADC and controller channels as well as the controller tables"};
// These are actually coming from the base config
ctk::ScalarPollInput<double> rfFrequency{
this, "rfFrequency", "MHz", "Working RF frequency of the system. Must be constant."};
ctk::ScalarPollInput<double> clockFrequency{
this, "clockFrequency", "MHz", "FPGA clock frequency (= raw ADC frequency). Must be constant."};
ctk::ScalarPollInput<uint32_t> IQdetectionLength{
this, "IQdetectionLength", "", "Number of raw ADC samples per IQ sample pair. Must be constant."};
// Runtime configuration from control system, global for entire server
ctk::ScalarPushInput<uint32_t> samplingDecimation{this, "samplingDecimation", "",
"Decimation factor to reduce amplitude/phase resp. I/Q data transferred from the FPGA to the CPU. This "
"allows to cover longer time periods at the cost of a lower sampling rate.",
{"DAQ"}};
// Global sampling position for display of individual samples (of all ADC and controller DAQ channels)
struct SamplingPosition : ctk::VariableGroup {
@@ -34,11 +43,27 @@ struct SamplingScheme : public ctk::ApplicationModule {
};
SamplingPosition samplingPosition{this, "SamplingPosition", ""};
// computed values
ctk::ScalarOutput<double> samplingFrequencyFilter{this, "samplingFrequencyFilter", "MHz",
"IQ sampling frequency as used for the IIR filters (i.e. the actual internal IQ sample frequency)"};
ctk::ScalarOutput<double> samplingFrequency{this, "samplingFrequency", "MHz",
"IQ sampling frequency as used for the ADC and controller channels as well as the controller tables"};
ctk::ScalarOutput<double> samplingTime{this, "samplingTime", "us", "Inverse of samplingFrequency"};
ctk::ScalarOutput<double> windowLength{
this, "windowLength", "ms", "Window length of ADC/controller data and tables"};
// Indices for flattop start and end (used in other modules)
ctk::ScalarOutput<uint32_t> flattopBeginIndex{this, "flattopBeginIndex", "", "Sample index of flattop start"};
ctk::ScalarOutput<uint32_t> flattopEndIndex{this, "flattopEndIndex", "", "Sample index of flattop end"};
} c{this, "/Configuration", ""};
// Frequency dividers to control various sampling frequencies in firmware
// Note: timingDividerAdc is managed by the DaqTriggerMux.
ctk::ScalarOutput<uint32_t> timingDividerController{
this, "timingDividerController", "", "Frequency divider used for controller DAQ"};
ctk::ScalarOutput<uint32_t> timingDividerTables{
this, "timingDividerTables", "", "Frequency divider used for control tables"};
// Input from Controller/TableGeneration: outer pulse shape
struct PulseShape : ctk::VariableGroup {
using ctk::VariableGroup::VariableGroup;
@@ -51,46 +76,3 @@ struct SamplingScheme : public ctk::ApplicationModule {
void mainLoop() override;
};
/**********************************************************************************************************************/
/**
* Extend pulse / ADC window duration by sampling decimation.
*/
struct WindowLengthSetter : ctk::ApplicationModule {
using ctk::ApplicationModule::ApplicationModule;
size_t pulseLength{appConfig().get<uint32_t>("Configuration/pulseLength")};
// Typically configuration constants from base_config.xml file
uint32_t IQdetectionLength{appConfig().get<uint32_t>("Configuration/IQdetectionLength")};
double clockFrequency{appConfig().get<double>("Configuration/clockFrequency")};
double rfFrequency{appConfig().get<double>("Configuration/rfFrequency")};
// Runtime configuration from control system, global for entire server
ctk::ScalarPushInput<uint32_t> samplingDecimation{this, "/Configuration/samplingDecimation", "",
"Decimation factor to reduce amplitude/phase resp. I/Q data transferred from the FPGA to the CPU. This "
"allows to cover longer time periods at the cost of a lower sampling rate.",
{"DAQ"}};
// computed values
ctk::ScalarOutput<double> samplingFrequencyFilter{this, "/Configuration/samplingFrequencyFilter", "MHz",
"IQ sampling frequency as used for the IIR filters (i.e. the actual internal IQ sample frequency)"};
ctk::ScalarOutput<double> samplingFrequency{this, "/Configuration/samplingFrequency", "MHz",
"IQ sampling frequency as used for the ADC and controller channels as well as the controller tables"};
ctk::ScalarOutput<double> samplingTime{this, "/Configuration/samplingTime", "us", "Inverse of samplingFrequency"};
ctk::ScalarOutput<double> windowLength{
this, "/Configuration/windowLength", "ms", "Window length of ADC/controller data and tables"};
// Frequency dividers to control various sampling frequencies in firmware
// Note: timingDividerAdc is managed by the DaqTriggerMux.
ctk::ScalarOutput<uint32_t> timingDividerController{
this, "/SamplingScheme/timingDividerController", "", "Frequency divider used for controller DAQ"};
ctk::ScalarOutput<uint32_t> timingDividerTables{
this, "/SamplingScheme/timingDividerTables", "", "Frequency divider used for control tables"};
void mainLoop() override;
void prepare() override;
};
/**********************************************************************************************************************/

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