Commit 497b6d58 authored by kvas's avatar kvas
Browse files

added latest version of the packet_generator

git-svn-id: https://svnsrv.desy.de/desy/ScCalo_DAQ/wing-lda/branches/packet_generator@329 dae6db90-30fc-4add-aa58-5bcfe2234c4d
parent 1c9c7bf2
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......@@ -90,6 +90,7 @@ architecture rtl of mem_man_axis_rx is
signal RX_WORD64_local : std_logic_vector(63 downto 0); -- selected word from the big 64-bit wide RX_MEM_DATA_local, degreyed version orheader
-- signal RX_SOP_local : std_logic; --local signal for Start of the packet
signal RX_EOP_local : std_logic; --local signal for End of the packet
signal RX_KEEP_local : std_logic_vector(2 downto 0); --local signal for tkeep signal for the last packet. word-wise
-- fifo write signals
signal fifo_din : std_logic_vector(67 downto 0); --TKEEP(3 downto 1) & TLAST & TDATA(63 downto 0)
......@@ -125,6 +126,7 @@ architecture rtl of mem_man_axis_rx is
signal RX_data : std_logic_vector(63 downto 0);
-- signal GPIO_RX_SOP :std_logic;
signal RX_EOP : std_logic;
signal RX_KEEP : std_logic_vector(2 downto 0);
signal ERROR_MC_RX_QUEUE_FULL : std_logic; -- when the queue is full
......@@ -199,7 +201,7 @@ begin
);
fifo_din(63 downto 0) <= RX_data;
fifo_din(64) <= RX_EOP; --wil be the tlast signal for the axi
fifo_din(67 downto 65) <= "111"; --TODO
fifo_din(67 downto 65) <= RX_KEEP; --"111"; --TODO
RX_AXIS_S2MM_tdata <= fifo_dout(63 downto 0);
RX_AXIS_S2MM_tkeep <= fifo_dout(67)&fifo_dout(67) & fifo_dout(66)&fifo_dout(66) & fifo_dout(65)&fifo_dout(65) & "11";
......@@ -367,6 +369,12 @@ begin
RX_WORD64_local <= (RX_STATUS_local & RX_PORT_local & RX_LDA_ID & X"00" & RX_CYCLE_local & RX_LENGTH_local(14 downto 0) &"0") when (rx_header_selector = '1') else
RX_degrayed when ((rx_degraying = '1') and (unsigned(RX_counter) /= 0)) else
RX_MEM_DATA_local; --when (rx_header_selector = '0') else
RX_KEEP_local <= "111" when RX_length_match = '0' else
"011" when (RX_LENGTH_local(1 downto 0) = "11") else
"001" when (RX_LENGTH_local(1 downto 0) = "10") else
"000" when (RX_LENGTH_local(1 downto 0) = "01") else
"111"; -- when (RX_LENGTH_local(1 downto) = "00") else
-- RX_WORD16_local <= RX_MEM_DATA_local(15 downto 0) when (RX_word16_bypass = '0') and (RX_counter(1 downto 0) = "00") else
-- RX_MEM_DATA_local(31 downto 16) when (RX_word16_bypass = '0') and (RX_counter(1 downto 0) = "01") else
......@@ -378,7 +386,7 @@ begin
-- RX_ADDR_local when (RX_word16_bypass = '1') and (RX_word16_alternative_selector = "11") else
-- (others => '-');
--RX_LAST_INTRAWORD <= '1' when RX_counter(1 downto 0) = "11" else '0'; -- the last intraword is readed when the last 2 digits point to the 4th word from the 64-bit wide word
--RX_LAST_INTRAWORD <= '1' when RX_counter(1 downto 0) = "11" else '0'; -- the last intraword is readed when the last 2 digits point to the 4th word from the 64-bit wide word
--counter of the transmitted number of words
RX_counter_proc : process(clk)
......@@ -424,12 +432,14 @@ begin
RX_EOP <= '0';
RX_DATA <= (others => '0');
fifo_WE_reg <= '0';
RX_KEEP <= (others => '1');
else
fifo_WE_reg <= fifo_WE;
if fifo_WE = '1' then
-- GPIO_RX_SOP <= RX_SOP_local;
RX_EOP <= RX_EOP_local;
RX_DATA <= RX_WORD64_local;
RX_KEEP <= RX_KEEP_local;
end if;
end if;
end if;
......@@ -547,106 +557,4 @@ begin
end case;
end process;
--==========================================================================
-- state machine for fetching the data from the memory to gpio FIFO
--==========================================================================
--==========================================================================
-- clk_gpio_proc:process(clk_gpio)
-- begin
-- if rising_edge(clk_gpio) then
-- reset_reg2 <= reset_reg1;
-- reset_reg1 <= reset;
-- if reset_reg2 = '1' then
-- gpio_state <= gpio_nodata;-- before debugging <= gpio_confirmed;
-- GPIO_RX_HSI_reg1 <= '0';
-- GPIO_RX_HSI_reg2 <= '0';
-- GPIO_RX_HSO <= '0';
-- gpio_debug_cnt <= (others => '0');
-- else
-- gpio_state <= gpio_next_state;
-- GPIO_RX_HSI_reg2 <= GPIO_RX_HSI_reg1;
-- GPIO_RX_HSI_reg1 <= GPIO_RX_HSI;
-- GPIO_RX_HSO <= GPIO_RX_HSO_int;
-- if (gpio_test_sw = '1') then
-- GPIO_RX_UDO(gpio_debug_cnt'range) <= std_logic_vector(gpio_debug_cnt);
-- GPIO_RX_UDO(GPIO_RX_UDO'high downto gpio_debug_cnt'high+1) <= (others => '0');
-- else
-- if GPIO_fifo_RE = '1' then
-- GPIO_RX_UDO <= swap16(GPIO_fifo_dout); --store the previous valid data
-- end if;
-- end if;
-- if (gpio_debug_cnt_inc = '1') then
-- gpio_debug_cnt <= gpio_debug_cnt + 1;
-- end if;
-- end if;
-- end if; --clk
-- end process;
-- gpio_next_state_proc:process( gpio_state, GPIO_RX_HSI_reg2, GPIO_fifo_valid, gpio_test_sw )--idle, fw1, fw2,fetch,h1, h2, h3, h4, write);
-- begin
-- case gpio_state is
-- when gpio_nodata =>
-- if (gpio_test_sw = '1') then
-- gpio_next_state <= gpio_ready; --debug --sends a debug counter out
-- else
-- if (GPIO_fifo_valid = '1') then
-- gpio_next_state <= gpio_ready;
-- else
-- gpio_next_state <= gpio_nodata;
-- end if;
-- end if;--gpio_test_sw
-- when gpio_ready =>
-- if (GPIO_RX_HSI_reg2 = '1') then
-- gpio_next_state <= gpio_sent;
-- else
-- gpio_next_state <= gpio_ready;
-- end if;
-- when gpio_sent =>
-- if (GPIO_RX_HSI_reg2 = '0') then
-- if gpio_test_sw = '1' then
-- gpio_next_state <= gpio_nodata; --debug
-- else
-- if (GPIO_fifo_valid = '1') then
-- gpio_next_state <= gpio_ready;
-- else
-- gpio_next_state <= gpio_nodata;
-- end if;
-- end if; --gpio_test_sw
-- else
-- gpio_next_state <= gpio_sent;
-- end if;
-- when others => gpio_next_state <= gpio_nodata;
-- end case;
-- end process;
---- GPIO_RX_UDO <= GPIO_fifo_dout;
-- gpio_out_proc:process( gpio_state, GPIO_RX_HSI_reg2, GPIO_fifo_valid, gpio_test_sw )--idle, fw1, fw2,fetch,h1, h2, h3, h4, write);
-- begin
-- GPIO_fifo_RE <= '0';
-- GPIO_RX_HSO_int <= '0';
-- gpio_debug_cnt_inc <= '0';
-- case gpio_state is
-- when gpio_nodata =>
-- if (gpio_test_sw = '1') then
-- gpio_debug_cnt_inc <= '1';
-- end if;
-- if (GPIO_fifo_valid = '1') then
-- GPIO_fifo_RE <= '1';
-- GPIO_RX_HSO_int <= '1';
-- end if;
-- when gpio_ready =>
-- GPIO_RX_HSO_int <= '1';
-- when gpio_sent =>
-- if (GPIO_RX_HSI_reg2 = '0') then
-- if (GPIO_fifo_valid = '1') then
-- GPIO_fifo_RE <= '1';
-- GPIO_RX_HSO_int <= '1';
-- end if;
-- end if;
-- when others =>
-- end case;
-- end process;
end rtl;
......@@ -912,6 +912,12 @@ begin
SYS_CONF_POINTER(47 downto 32) <= SYS_POINTER_STATUS_reg;
SYS_CONF_POINTER(63 downto 48) <= roc_counter;
SYS_status(15 downto 0) <= DIF_BUSY(15 downto 0); --TODO only 16 busys, must use all
sys_stat_gen : if PORTS_NUMBER < 16 generate
SYS_status(PORTS_NUMBER-1 downto 0) <= DIF_BUSY(PORTS_NUMBER-1 downto 0);
end generate sys_stat_gen;
sys_stat_gen2 : if PORTS_NUMBER > 15 generate
SYS_status(15 downto 0) <= DIF_BUSY(15 downto 0); --TODO only 16 busys, must use all
end generate sys_stat_gen2;
end struct;
......@@ -36,8 +36,9 @@ use xil_defaultlib.lda_pkg.all;
entity klink_ctrl is
generic (
KINTEX : integer := 0;
IDELAY_DEFAULT : MARS_DEFAULT_IDELAYS_T := (others => 0)
KINTEX : integer := 0;
IDELAY_DEFAULT : MARS_DEFAULT_IDELAYS_T := (others => 0);
AXI_ALIGN_DATA : boolean := true
);
port (
clk : in std_logic; --system clock 40 MHz, BufG expected
......@@ -164,8 +165,9 @@ architecture rtl of klink_ctrl is
component lin_ctrl
generic (
MEM_SIZE : integer;
PORTS : integer);
MEM_SIZE : integer;
PORTS : integer;
AXI_ALIGN_DATA : boolean);
port (
clk : in std_logic;
rst : in std_logic;
......@@ -284,8 +286,9 @@ begin
lin_ctrl_1 : lin_ctrl
generic map (
MEM_SIZE => 15,
PORTS => IPORTS)
MEM_SIZE => 15,
PORTS => IPORTS,
AXI_ALIGN_DATA => AXI_ALIGN_DATA)
port map (
clk => clk,
rst => rst,
......
......@@ -34,8 +34,9 @@ use IEEE.NUMERIC_STD.all;
entity lin_ctrl is
generic (
MEM_SIZE : integer := 15; -- size of the internal buffer memory used for retransmission
PORTS : integer := 2
MEM_SIZE : integer := 15; -- size of the internal buffer memory used for retransmission
PORTS : integer := 2;
AXI_ALIGN_DATA : boolean := true
);
port (
......@@ -264,11 +265,6 @@ begin
end if;
end process;
--TODO to be implemented
--rx_tkeep <= keep3 & keep3 & keep2 & keep2 & keep1 & keep1 & "11";
rx_tkeep <= (others => '1');
rx_tstrb <= (others => '1');
rptr_proc : process(clk_axi)
begin
if rising_edge(clk_axi) then
......@@ -282,7 +278,17 @@ begin
end if;
end process;
rx_tdata_proc : process(doutb, keep1, keep2, keep3)
keep_gen1 : if AXI_ALIGN_DATA = true generate
rx_tkeep <= (others => '1');
rx_tstrb <= (others => '1');
end generate keep_gen1;
keep_gen0 : if AXI_ALIGN_DATA = false generate
rx_tkeep <= keep3 & keep3 & keep2 & keep2 & keep1 & keep1 & "11";
rx_tstrb <= keep3 & keep3 & keep2 & keep2 & keep1 & keep1 & "11";
end generate keep_gen0;
rx_tdata_proc : process(doutb, keep1, keep2, keep3) --transmit only data, that should be kept. Rest => 0
begin
rx_tdata <= doutb;
if keep1 = '0' then
......
......@@ -34,7 +34,8 @@ use UNISIM.VComponents.all;
entity mars_pl is
generic (
KINTEXES : integer := 2 --number of connected slave FPGAs
KINTEXES : integer := 2; --number of connected slave FPGAs
AXI_ALIGN_DATA : boolean := true
);
port (
FCLK_CLK0 : in std_logic; -- 100 MHz clk generated by the PS, used for AXI-Stream
......@@ -127,7 +128,8 @@ architecture rtl of mars_pl is
component klink_ctrl
generic (
KINTEX : integer;
IDELAY_DEFAULT : MARS_DEFAULT_IDELAYS_T := (others => 0)
IDELAY_DEFAULT : MARS_DEFAULT_IDELAYS_T := (others => 0);
AXI_ALIGN_DATA : boolean := true
);
port (
clk : in std_logic;
......@@ -336,7 +338,7 @@ begin
KINTEXES => KINTEXES,
SIZE_SRC => 2,
SIZE_DEST => 8,
AXI_ALIGN_DATA => true)
AXI_ALIGN_DATA => AXI_ALIGN_DATA)
port map (
clk => clk, --ok
clk_axi => clk_axi, --ok
......@@ -512,7 +514,8 @@ begin
klink_ctrl_inst : klink_ctrl
generic map (
KINTEX => i,
IDELAY_DEFAULT => MARS_DEFAULT_IDELAYS(i))
IDELAY_DEFAULT => MARS_DEFAULT_IDELAYS(i),
AXI_ALIGN_DATA => AXI_ALIGN_DATA)
port map (
clk => clk,
clk_200 => clk_200_G,
......
This diff is collapsed.
......@@ -33,7 +33,8 @@ use UNISIM.VComponents.all;
entity mars_top is
generic (
KINTEXES : integer := 2 --number of connected slave FPGAs
KINTEXES : integer := 2; --number of connected slave FPGAs
AXI_ALIGN_DATA : boolean := true
);
port (
--==========================================================================
......@@ -226,7 +227,8 @@ architecture rtl of mars_top is
--end component mars_ps;
component mars_pl is
generic (
KINTEXES : integer := 1 --number of connected slave FPGAs
KINTEXES : integer := 1; --number of connected slave FPGAs
AXI_ALIGN_DATA : boolean := true
);
port (
FCLK_CLK0 : in std_logic; -- 100 MHz clk generated by the PS, used for AXI-Stream
......@@ -340,7 +342,8 @@ begin
mars_pl_inst : mars_pl
generic map (
KINTEXES => KINTEXES --number of connected slave FPGAs
KINTEXES => KINTEXES, --number of connected slave FPGAs
AXI_ALIGN_DATA => AXI_ALIGN_DATA
)
port map(
FCLK_CLK0 => FCLK_CLK0 ,
......
......@@ -357,7 +357,8 @@ begin
else
next_state <= s_idle;
end if;
when others => null;
when others =>
next_state <= s_idle;
end case;
end process;
......
......@@ -155,7 +155,7 @@ architecture Behavioral of mars_pl_tbio is
begin
ENC8B10B_1 : ENC8B10B
port map (
CLK_IN => CCC_HDMI_CLK,
CLK_IN => FCLK_CLK1,
RUNDP_RESET_IN => user_reset,
CTRL_IN => enc_CTRL_IN(0),
DATA_IN => enc_DATA_IN(7 downto 0),
......@@ -163,7 +163,7 @@ begin
ENCODE_OUT => ENCODE_OUT(9 downto 0));
ENC8B10B_2 : ENC8B10B
port map (
CLK_IN => CCC_HDMI_CLK,
CLK_IN => FCLK_CLK1,
RUNDP_RESET_IN => user_reset,
CTRL_IN => enc_CTRL_IN(1),
DATA_IN => enc_DATA_IN(15 downto 8),
......@@ -245,9 +245,9 @@ begin
fake_k2z_gen : process
variable out_data : std_logic_vector(ENCODE_OUT'range);
begin
wait until rising_edge(CCC_HDMI_CLK);
wait until rising_edge(FCLK_CLK1);
wait for 1 ns; --some time after the clock edge
wait for 8*2.5 ns; --to be aligned with the 40MHz clock
wait for 6*2.5 ns; --to be aligned with the 40MHz clock
while true loop
out_data := ENCODE_OUT;
for i in 9 downto 0 loop
......@@ -260,7 +260,7 @@ begin
end loop;
end process;
fake_k2z_link : process
variable cnt : unsigned(31 downto 0) := (others => '0');
......@@ -271,7 +271,7 @@ begin
begin
enc_DATA_IN <= cdataw(15 downto 0);
enc_CTRL_IN <= cdataw(17 downto 16);
wait until rising_edge(CCC_HDMI_CLK);
wait until rising_edge(FCLK_CLK1);
enc_DATA_IN <= SEQ_IDLE(15 downto 0); --reset to default idle
enc_CTRL_IN <= SEQ_IDLE(17 downto 16);
end k2z_put;
......@@ -280,6 +280,96 @@ begin
enc_DATA_IN <= SEQ_IDLE(15 downto 0);
S_AXIS_S2MM_tready <= '1';
wait for 3000 ns;
for i in 0 to 10 loop
k2z_put(SEQ_FSTART);
k2z_put("00" & X"000E");
k2z_put("00" & X"0000");
k2z_put("00" & X"000B");
k2z_put("00" & X"2002");
k2z_put("00" & X"CC02");
k2z_put("00" & X"0F0F");
k2z_put("00" & X"0070");
k2z_put("00" & X"2100");
k2z_put("00" & X"0001");
k2z_put("00" & X"0000");
k2z_put("00" & X"ABAB");
k2z_put("00" & X"4C77");
k2z_put(SEQ_FEND);
-- wait for i*1000 ns;
k2z_put(SEQ_FSTART);
k2z_put("00" & X"0010");
k2z_put("00" & X"0000");
k2z_put("00" & X"000B");
k2z_put("00" & X"2002");
k2z_put("00" & X"CC02");
k2z_put("00" & X"0F0F");
k2z_put("00" & X"0070");
k2z_put("00" & X"2100");
k2z_put("00" & X"0002");
k2z_put("00" & X"0000");
k2z_put("00" & X"0001");
k2z_put("00" & X"ABAB");
k2z_put("00" & X"67CD");
k2z_put(SEQ_FEND);
-- wait for i*1000 ns;
k2z_put(SEQ_FSTART);
k2z_put("00" & X"0012");
k2z_put("00" & X"0000");
k2z_put("00" & X"000B");
k2z_put("00" & X"2002");
k2z_put("00" & X"CC02");
k2z_put("00" & X"0F0F");
k2z_put("00" & X"0070");
k2z_put("00" & X"2100");
k2z_put("00" & X"0003");
k2z_put("00" & X"0000");
k2z_put("00" & X"0001");
k2z_put("00" & X"0002");
k2z_put("00" & X"ABAB");
k2z_put("00" & X"D197");
k2z_put(SEQ_FEND);
-- wait for i*1000 ns;
k2z_put(SEQ_FSTART);
k2z_put("00" & X"0014");
k2z_put("00" & X"0000");
k2z_put("00" & X"000B");
k2z_put("00" & X"2002");
k2z_put("00" & X"CC02");
k2z_put("00" & X"0F0F");
k2z_put("00" & X"0070");
k2z_put("00" & X"2100");
k2z_put("00" & X"0004");
k2z_put("00" & X"0000");
k2z_put("00" & X"0001");
k2z_put("00" & X"0002");
k2z_put("00" & X"0003");
k2z_put("00" & X"ABAB");
k2z_put("00" & X"E25A");
k2z_put(SEQ_FEND);
-- wait for i*1000 ns;
k2z_put(SEQ_FSTART);
k2z_put("00" & X"0016");
k2z_put("00" & X"0000");
k2z_put("00" & X"000B");
k2z_put("00" & X"2002");
k2z_put("00" & X"CC02");
k2z_put("00" & X"0F0F");
k2z_put("00" & X"0070");
k2z_put("00" & X"2100");
k2z_put("00" & X"0005");
k2z_put("00" & X"0000");
k2z_put("00" & X"0001");
k2z_put("00" & X"0002");
k2z_put("00" & X"0003");
k2z_put("00" & X"0004");
k2z_put("00" & X"ABAB");
k2z_put("00" & X"DFD2");
k2z_put(SEQ_FEND);
-- wait for i*1000 ns;
-- wait for 2000 ns;
end loop; -- i
for i in 0 to 100 loop
wait for 400 ns;
k2z_put(SEQ_NACK);
......@@ -291,8 +381,8 @@ begin
fake_axi_sender : process
variable cnt : unsigned(31 downto 0) := (others => '0');
--random number generator signals
variable seed1, seed2 : positive; -- Seed values for the random generator
variable rand : real; -- Random value (0 to 1.0 range)
variable seed1, seed2 : positive; -- Seed values for the random generator
variable rand : real; -- Random value (0 to 1.0 range)
procedure SEND(constant dataw : in std_logic_vector(31 downto 0); constant tkeep : in std_logic_vector(3 downto 0); constant tlast : in std_logic; constant delay : in real) is -- delay is in ns and is random
begin
wait until falling_edge(FCLK_CLK0);
......@@ -302,11 +392,11 @@ begin
M_AXIS_MM2S_tvalid <= '1';
wait until rising_edge(FCLK_CLK0);
while M_AXIS_MM2S_tready = '0' loop
wait until rising_edge(FCLK_CLK0); -- wait for axi_period until ready;
wait until rising_edge(FCLK_CLK0); -- wait for axi_period until ready;
end loop;
M_AXIS_MM2S_tvalid <= '0';
UNIFORM(seed1, seed2, rand);
wait for axi_period * integer(trunc(rand * delay)); -- wait for random number of clock cycles
wait for axi_period * integer(trunc(rand * delay)); -- wait for random number of clock cycles
end SEND;
begin
M_AXIS_MM2S_tdata <= (others => '0');
......@@ -315,17 +405,17 @@ begin
M_AXIS_MM2S_tkeep <= (others => '0');
wait for 3000 ns;
--send a broadcast packet
SEND((X"0000000C"), "1111", '0', 00.0); --number of bytes
SEND((X"0F0FFF02"), "1111", '0', 00.0); --broadcast (FF)
SEND((X"00040012"), "1111", '0', 00.0); -- some power on cmd to DIF
SEND((X"ABAB0000"), "1111", '1', 00.0); -- null data,ABAB
wait for 1000 ns;
SEND((X"0000000C"), "1111", '0', 00.0); --number of bytes
SEND((X"0F0FFF02"), "1111", '0', 00.0); --broadcast (FF)
SEND((X"00040012"), "1111", '0', 00.0); -- some power on cmd to DIF
SEND((X"ABAB0000"), "1111", '1', 00.0); -- null data,ABAB
wait for 1000 ns;
wait;
--start the packet generator
SEND((X"00000008"), "1111", '0', 00.0); --number of bytes
SEND((X"90008302"), "1111", '0', 00.0); --broadcast (FF)
SEND((X"ABAB0010"), "1111", '1', 00.0); -- some power on cmd to DIF
wait for 1000 ns;
SEND((X"00000008"), "1111", '0', 00.0); --number of bytes
SEND((X"90008302"), "1111", '0', 00.0); --broadcast (FF)
SEND((X"ABAB0010"), "1111", '1', 00.0); -- some power on cmd to DIF
wait for 1000 ns;
for i in 0 to 97 loop
......
......@@ -10,12 +10,12 @@ set_property IOSTANDARD LVCMOS25 [get_ports {Led_N[*]}]
# ------------------------------------------------
# -- i2-port
## ------------------------------------------------
#set_property PACKAGE_PIN H15 [get_ports I2C0_SDA]
#set_property IOSTANDARD LVCMOS25 [get_ports I2C0_SDA]
# ------------------------------------------------
set_property PACKAGE_PIN H15 [get_ports I2C0_SDA]
set_property IOSTANDARD LVCMOS25 [get_ports I2C0_SDA]
#set_property PACKAGE_PIN R15 [get_ports I2C0_SCL]
#set_property IOSTANDARD LVCMOS25 [get_ports I2C0_SCL]
set_property PACKAGE_PIN R15 [get_ports I2C0_SCL]
set_property IOSTANDARD LVCMOS25 [get_ports I2C0_SCL]
#set_property PACKAGE_PIN H17 [get_ports I2C0_INT_N]
#set_property IOSTANDARD LVCMOS25 [get_ports I2C0_INT_N]
......
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