added logic.c/h

pilc2_functions/pilc2_logic.c

+
+#include "pilc2_register_func.h"
+#include "pilc2_logic.h"
+#include <stdio.h>
+
+
+int setLogicInvertEn(unsigned int channel, unsigned int IO) {
+	unsigned int reg;
+	unsigned int mask = 0x1;
+	
+	reg = ReadFPGA(PILC_LOGIC_OFFSET+PILC_LOGIC_CFG_OFFSET+channel);
+	
+	WriteFPGA(PILC_LOGIC_OFFSET+PILC_LOGIC_CFG_OFFSET+channel, reg|mask<<IO);
+	
+	return 0;
+}
+
+int setLogicInvertDis(unsigned int channel, unsigned int IO) {
+	unsigned int reg;
+	unsigned int mask = 0x1;
+	
+	reg = ReadFPGA(PILC_LOGIC_OFFSET+PILC_LOGIC_CFG_OFFSET+channel);
+	
+	WriteFPGA(PILC_LOGIC_OFFSET+PILC_LOGIC_CFG_OFFSET+channel, reg&~mask<<IO);
+	
+	return 0;
+}
+
+int setLogic(unsigned int channel, unsigned int IO, unsigned int value) {
+	unsigned int reg;
+	unsigned int ABmask = 0xFF00;
+	unsigned int ABCmask = 0xFF0000;
+	
+	reg = ReadFPGA(PILC_LOGIC_OFFSET+PILC_LOGIC_CFG_OFFSET+channel);
+	
+	if (IO == LOGIC_IO_AB){
+		if (value == 0) {
+			WriteFPGA(PILC_LOGIC_OFFSET+PILC_LOGIC_CFG_OFFSET+channel, reg&~(ABmask|ABCmask));
+		}else {
+			WriteFPGA(PILC_LOGIC_OFFSET+PILC_LOGIC_CFG_OFFSET+channel, reg|((value<<LOGIC_IO_AB)&ABmask));
+			
+		}
+	} else if (IO == LOGIC_IO_ABC) {
+		if ( (reg & ABmask) != 0) {
+			if (value == 0) {
+				WriteFPGA(PILC_LOGIC_OFFSET+PILC_LOGIC_CFG_OFFSET+channel, reg&~ABCmask);
+			} else {
+				WriteFPGA(PILC_LOGIC_OFFSET+PILC_LOGIC_CFG_OFFSET+channel, reg|((value<<LOGIC_IO_ABC)&ABCmask));
+			}
+		}else {
+			return -1;
+		}
+	}
+	
+	return 0;
+}
+
+
+int setLogicCfg(unsigned int channel, unsigned int config) {
+	unsigned int ABmask = 0xFF00;
+	unsigned int ABCmask = 0xFF0000;
+	
+	/*check if config is valid*/
+	if ((config & ABmask) == 0 && (config & ABCmask) != 0) {
+		return -1;
+	}else{
+		WriteFPGA(PILC_LOGIC_OFFSET+PILC_LOGIC_CFG_OFFSET+channel, config);
+	}
+	
+	return 0;
+}
+
+unsigned int GetLogicCfg(unsigned int channel) {
+	unsigned int value;
+	
+	value = ReadFPGA(PILC_LOGIC_OFFSET+PILC_LOGIC_CFG_OFFSET+channel);
+	
+	return value;
+}
+
+
+int setLogicDly(unsigned int channel, unsigned int delay) {
+	WriteFPGA(PILC_LOGIC_OFFSET+PILC_LOGIC_DLY_OFFSET+channel, delay);
+	
+	return 0;
+}
+
+
+
+int GetLogicDly(unsigned int channel, unsigned int delay) {
+	unsigned int value;
+	
+	value = ReadFPGA(PILC_LOGIC_OFFSET+PILC_LOGIC_DLY_OFFSET+channel);
+	
+	return value;
+}

pilc2_functions/pilc2_logic.h

+
+
+
+#define     PILC_LOGIC_OFFSET		(0x10000>>2)
+#define     PILC_LOGIC_CFG_OFFSET	0x0
+#define     PILC_LOGIC_DLY_OFFSET	0x4
+
+#define		LOGIC_CH_0		0x0
+#define		LOGIC_CH_1		0x1
+#define		LOGIC_CH_2		0x2
+#define		LOGIC_CH_3		0x3
+
+#define 	LOGIC_IO_A			0x0
+#define 	LOGIC_IO_B			0x1
+#define 	LOGIC_IO_C			0x2
+#define 	LOGIC_IO_Y			0x3
+
+#define 	LOGIC_IO_AB			0x8
+#define		LOGIC_IO_ABC		0x10
+
+#define 	LOGIC_CFG_CH_0		0x0
+#define 	LOGIC_CFG_CH_1		0x1
+#define 	LOGIC_CFG_CH_2		0x2
+#define 	LOGIC_CFG_CH_3		0x3
+
+#define 	LOGIC_DLY_CH_0		0x4
+#define 	LOGIC_DLY_CH_1		0x5
+#define 	LOGIC_DLY_CH_2		0x6
+#define 	LOGIC_DLY_CH_3		0x7
+
+#define		INV_EN				0x1
+#define		INV_DIS				0x0
+
+#define		LOGIC_OR			0x1
+#define		LOGIC_AND			0x2
+#define		LOGIC_XOR			0x3
+
+
+int setLogicInvertEn(unsigned int channel, unsigned int IO);
+int setLogicInvertDis(unsigned int channel, unsigned int IO);
+int setLogic(unsigned int channel, unsigned int IO, unsigned int value);
+int setLogicCfg(unsigned int channel, unsigned int config);
+int setLogicDly(unsigned int channel, unsigned int delay);
+
+unsigned int GetLogicCfg(unsigned int channel);
+int GetLogicDly(unsigned int channel, unsigned int delay);