changes in #define naming

pilc2_functions/pilc2_IO_GPIOs.c

@@ -466,10 +466,10 @@ void getNIMTTLcolour(int card_slot, led_color_struct *led_color) {
 		/* If logic mode is selected it is possible to not use all inputs, 
 		 * therefore only leds for enabled inputs have to be enabled */	
 		case IO_MUX_CFG_LOGIC:
-			if (card_slot < 16) logicfg = GetLogicCfg(LOGIC_CFG_CH_3);
-			if (card_slot < 12) logicfg = GetLogicCfg(LOGIC_CFG_CH_2);
-			if (card_slot < 8) logicfg = GetLogicCfg(LOGIC_CFG_CH_1);
-			if (card_slot < 4) logicfg = GetLogicCfg(LOGIC_CFG_CH_0);
+			if (card_slot < 16) logicfg = GetLogicCfg(LOGIC_CH_3);
+			if (card_slot < 12) logicfg = GetLogicCfg(LOGIC_CH_2);
+			if (card_slot < 8) logicfg = GetLogicCfg(LOGIC_CH_1);
+			if (card_slot < 4) logicfg = GetLogicCfg(LOGIC_CH_0);
 			switch (card_slot % 4) {
 				case 0:	
 					led_color->Green = 8; 

pilc2_functions/pilc2_IO_GPIOs.h

@@ -17,6 +17,7 @@
 
 #define PiLC_IOSTR 0x00
 #define PiLC_IODDR 0x01
+#define PILC_IODDR_CFG_REG  0x1
 #define PiLC_Projekt 0x02
 #define PiLC_PVersion 0x03
 #define PiLC_HVersion 0x04
@@ -48,7 +49,7 @@
 #define IO_CH_14		0x4000
 #define IO_CH_15		0x8000
 
-#define PILC_IODDR_CFG_REG  0x1
+
 
 #define PILC_IO_INPUT	0x0
 #define PILC_IO_OUTPUT	0x1

pilc2_functions/pilc2_IO_Leds.c

@@ -29,7 +29,7 @@
 void WriteFrontLED (unsigned char LED, unsigned char Red, unsigned char Green,
 				unsigned char Blue)
 {
-	WriteFPGA(FP_LED_OFFSET+LED, Blue<<16|Red<<8|Green);
+	WriteFPGA(PILC_FP_LED_OFFSET+LED, Blue<<16|Red<<8|Green);
 }
 
 /******************************************************************************/
@@ -63,7 +63,7 @@ int deinit_IOleds(void)
 *******************************************************************************/
 void InhibitFrontLED(unsigned int led_mask) 
 {
-	WriteFPGA(FP_LED_OFFSET+FP_LED_INHIBIT, led_mask);
+	WriteFPGA(PILC_FP_LED_OFFSET+FP_LED_INHIBIT, led_mask);
 }
 
 

pilc2_functions/pilc2_IO_Leds.h

@@ -9,26 +9,26 @@
 
 /*************************** Constant Definitions *****************************/
 
-#define FP_LED_OFFSET 	(0x300>>2)
+#define PILC_FP_LED_OFFSET 	(0x300>>2)
 
-#define FP_LED_0 		FP_LED_OFFSET+0x0
-#define FP_LED_1 		FP_LED_OFFSET+0x1
-#define FP_LED_2 		FP_LED_OFFSET+0x2
-#define FP_LED_3 		FP_LED_OFFSET+0x3
-#define FP_LED_4 		FP_LED_OFFSET+0x4
-#define FP_LED_5 		FP_LED_OFFSET+0x5
-#define FP_LED_6 		FP_LED_OFFSET+0x6
-#define FP_LED_7 		FP_LED_OFFSET+0x7
-#define FP_LED_8 		FP_LED_OFFSET+0x8
-#define FP_LED_9 		FP_LED_OFFSET+0x9
-#define FP_LED_10 		FP_LED_OFFSET+0xA
-#define FP_LED_11 		FP_LED_OFFSET+0xB
-#define FP_LED_12 		FP_LED_OFFSET+0xC
-#define FP_LED_13 		FP_LED_OFFSET+0xD
-#define FP_LED_14 		FP_LED_OFFSET+0xE
-#define FP_LED_15 		FP_LED_OFFSET+0xF
-#define FP_LED_16 		FP_LED_OFFSET+0x10
-#define FP_LED_17 		FP_LED_OFFSET+0x11
+#define FP_LED_0 		0x0
+#define FP_LED_1 		0x1
+#define FP_LED_2 		0x2
+#define FP_LED_3 		0x3
+#define FP_LED_4 		0x4
+#define FP_LED_5 		0x5
+#define FP_LED_6 		0x6
+#define FP_LED_7 		0x7
+#define FP_LED_8 		0x8
+#define FP_LED_9 		0x9
+#define FP_LED_10 		0xA
+#define FP_LED_11 		0xB
+#define FP_LED_12 		0xC
+#define FP_LED_13 		0xD
+#define FP_LED_14 		0xE
+#define FP_LED_15 		0xF
+#define FP_LED_16 		0x10
+#define FP_LED_17 		0x11
 #define FP_LED_INHIBIT 	0x12
 
 #define NUMBER_OF_LEDS 18

pilc2_functions/pilc2_IO_mux.h

@@ -13,22 +13,22 @@
 /*************************** Constant Definitions *****************************/
 #define PILC_IO_MUX_OFFSET		(0x8000>>2)
 
-#define PILC_IO_MUX_CFG_CH_0	0x0
-#define PILC_IO_MUX_CFG_CH_1	0x1
-#define PILC_IO_MUX_CFG_CH_2	0x2
-#define PILC_IO_MUX_CFG_CH_3	0x3
-#define PILC_IO_MUX_CFG_CH_4	0x4
-#define PILC_IO_MUX_CFG_CH_5	0x5
-#define PILC_IO_MUX_CFG_CH_6	0x6
-#define PILC_IO_MUX_CFG_CH_7	0x7
-#define PILC_IO_MUX_CFG_CH_8	0x8
-#define PILC_IO_MUX_CFG_CH_9	0x9
-#define PILC_IO_MUX_CFG_CH_10	0xA
-#define PILC_IO_MUX_CFG_CH_11	0xB
-#define PILC_IO_MUX_CFG_CH_12	0xC
-#define PILC_IO_MUX_CFG_CH_13	0xD
-#define PILC_IO_MUX_CFG_CH_14	0xE
-#define PILC_IO_MUX_CFG_CH_15	0xF
+#define IO_MUX_CFG_CH_0	0x0
+#define IO_MUX_CFG_CH_1	0x1
+#define IO_MUX_CFG_CH_2	0x2
+#define IO_MUX_CFG_CH_3	0x3
+#define IO_MUX_CFG_CH_4	0x4
+#define IO_MUX_CFG_CH_5	0x5
+#define IO_MUX_CFG_CH_6	0x6
+#define IO_MUX_CFG_CH_7	0x7
+#define IO_MUX_CFG_CH_8	0x8
+#define IO_MUX_CFG_CH_9	0x9
+#define IO_MUX_CFG_CH_10	0xA
+#define IO_MUX_CFG_CH_11	0xB
+#define IO_MUX_CFG_CH_12	0xC
+#define IO_MUX_CFG_CH_13	0xD
+#define IO_MUX_CFG_CH_14	0xE
+#define IO_MUX_CFG_CH_15	0xF
 
 #define IO_MUX_CFG_CTR			0x1
 #define IO_MUX_CFG_ADC			0x2

pilc2_functions/pilc2_adc.h

@@ -9,37 +9,37 @@
 
 /*************************** Constant Definitions *****************************/
 #define PILC_ADC_OFFSET		(0x3000>>2)
-#define ADC_FILTER_REG_OFFSET (0x0>>2)
-#define ADC_DATA_REG_OFFSET	(0x40>>2)
+#define ADC_FILTER_REG_OFFSET 	0x0
+#define ADC_DATA_REG_OFFSET		0x10
 
-#define PILC_ADC_DATA_CH_0			0x0
-#define PILC_ADC_DATA_CH_1			0x1
-#define PILC_ADC_DATA_CH_2			0x2
-#define PILC_ADC_DATA_CH_3			0x3
-#define PILC_ADC_DATA_CH_4			0x4
-#define PILC_ADC_DATA_CH_5			0x5
-#define PILC_ADC_DATA_CH_6			0x6
-#define PILC_ADC_DATA_CH_7			0x7
-#define PILC_ADC_DATA_CH_8			0x8
-#define PILC_ADC_DATA_CH_9			0x9
-#define PILC_ADC_DATA_CH_10			0xA
-#define PILC_ADC_DATA_CH_11			0xB
-#define PILC_ADC_DATA_CH_12			0xC
-#define PILC_ADC_DATA_CH_13			0xD
-#define PILC_ADC_DATA_CH_14			0xE
-#define PILC_ADC_DATA_CH_15			0xF
+#define ADC_DATA_CH_0			0x0
+#define ADC_DATA_CH_1			0x1
+#define ADC_DATA_CH_2			0x2
+#define ADC_DATA_CH_3			0x3
+#define ADC_DATA_CH_4			0x4
+#define ADC_DATA_CH_5			0x5
+#define ADC_DATA_CH_6			0x6
+#define ADC_DATA_CH_7			0x7
+#define ADC_DATA_CH_8			0x8
+#define ADC_DATA_CH_9			0x9
+#define ADC_DATA_CH_10			0xA
+#define ADC_DATA_CH_11			0xB
+#define ADC_DATA_CH_12			0xC
+#define ADC_DATA_CH_13			0xD
+#define ADC_DATA_CH_14			0xE
+#define ADC_DATA_CH_15			0xF
 
-#define	PILC_ADC_FILTER_1			0x1
-#define	PILC_ADC_FILTER_2			0x2
-#define	PILC_ADC_FILTER_4			0x3
-#define	PILC_ADC_FILTER_8			0x4
-#define	PILC_ADC_FILTER_16			0x5
-#define	PILC_ADC_FILTER_32			0x6
-#define	PILC_ADC_FILTER_64			0x7
-#define	PILC_ADC_FILTER_128			0x8
-#define	PILC_ADC_FILTER_256			0x9
-#define	PILC_ADC_FILTER_512			0xA
-#define	PILC_ADC_FILTER_1014		0xB
+#define	ADC_FILTER_1			0x1
+#define	ADC_FILTER_2			0x2
+#define	ADC_FILTER_4			0x3
+#define	ADC_FILTER_8			0x4
+#define	ADC_FILTER_16			0x5
+#define	ADC_FILTER_32			0x6
+#define	ADC_FILTER_64			0x7
+#define	ADC_FILTER_128			0x8
+#define	ADC_FILTER_256			0x9
+#define	ADC_FILTER_512			0xA
+#define	ADC_FILTER_1014		0xB
 
 
 /*************************** Function Prototypes ******************************/

pilc2_functions/pilc2_bram_controller.c

@@ -29,7 +29,7 @@
 ******************************************************************************/
 void PiLC2BRAMControllerConfigWrite(unsigned int config){
 	
-	WriteFPGA(PILC2_BRAM_CTRL_MOD_OFFSET+PILC2_BRAM_CTRL_CTRLREG_OFFSET, 
+	WriteFPGA(PILC2_BRAM_CTRL_MOD_OFFSET+BRAM_CTRL_CTRLREG_OFFSET, 
 			config);
 }
 
@@ -48,7 +48,7 @@ void PiLC2BRAMControllerConfigWrite(unsigned int config){
 unsigned int PiLC2BRAMControllerConfigRead(void){
 	unsigned int value;
 	
-	value = ReadFPGA(PILC2_BRAM_CTRL_MOD_OFFSET+PILC2_BRAM_CTRL_CTRLREG_OFFSET);
+	value = ReadFPGA(PILC2_BRAM_CTRL_MOD_OFFSET+BRAM_CTRL_CTRLREG_OFFSET);
 	
 	return value;
 }
@@ -69,11 +69,11 @@ unsigned int PiLC2BRAMControllerConfigRead(void){
 void PiLC2BRAMControllerResetBRAMcount(void){
 	
 	/* set reset bits */
-	WriteFPGA(PILC2_BRAM_CTRL_MOD_OFFSET+PILC2_BRAM_CTRL_CTRLREG_OFFSET, 
-			PILC2_BRAM_CFG_RESET_BRAM_CTR);
+	WriteFPGA(PILC2_BRAM_CTRL_MOD_OFFSET+BRAM_CTRL_CTRLREG_OFFSET, 
+			BRAM_CFG_RESET_BRAM_CTR);
 	
 	/* set all bits to 0 */		
-	WriteFPGA(PILC2_BRAM_CTRL_MOD_OFFSET+PILC2_BRAM_CTRL_CTRLREG_OFFSET, 
+	WriteFPGA(PILC2_BRAM_CTRL_MOD_OFFSET+BRAM_CTRL_CTRLREG_OFFSET, 
 			0x0);		
 }
 
@@ -92,11 +92,11 @@ void PiLC2BRAMControllerResetBRAMcount(void){
 void PiLC2BRAMControllerResetController(void){
 	
 	/* set reset bits */
-	WriteFPGA(PILC2_BRAM_CTRL_MOD_OFFSET+PILC2_BRAM_CTRL_CTRLREG_OFFSET, 
-			PILC2_BRAM_CFG_RESET_MODULE);
+	WriteFPGA(PILC2_BRAM_CTRL_MOD_OFFSET+BRAM_CTRL_CTRLREG_OFFSET, 
+			BRAM_CFG_RESET_MODULE);
 	
 	/* set all bits to 0 */		
-	WriteFPGA(PILC2_BRAM_CTRL_MOD_OFFSET+PILC2_BRAM_CTRL_CTRLREG_OFFSET, 
+	WriteFPGA(PILC2_BRAM_CTRL_MOD_OFFSET+BRAM_CTRL_CTRLREG_OFFSET, 
 			0x0);		
 }
 
@@ -116,7 +116,7 @@ void PiLC2BRAMControllerResetController(void){
 unsigned int PiLC2BRAMControllerRBRAMCount(void){
 	unsigned int value;
 	
-	value = ReadFPGA(PILC2_BRAM_CTRL_MOD_OFFSET+PILC2_BRAM_CTRL_WCOUNT_OFFSET);
+	value = ReadFPGA(PILC2_BRAM_CTRL_MOD_OFFSET+BRAM_CTRL_WCOUNT_OFFSET);
 	
 	return value;	
 }
@@ -137,7 +137,7 @@ unsigned int PiLC2BRAMControllerRFIFOCount(void){
 	unsigned int value;
 	
 	value = ReadFPGA(PILC2_BRAM_CTRL_MOD_OFFSET+
-					PILC2_BRAM_CTRL_FIFO_COUNT_OFFSET);
+					BRAM_CTRL_FIFO_COUNT_OFFSET);
 	
 	return value;
 }
@@ -157,8 +157,8 @@ unsigned int PiLC2BRAMControllerRFIFOCount(void){
 ******************************************************************************/
 void PiLC2BRAMControllerEnWBRAM(void){
 	
-	WriteFPGA(PILC2_BRAM_CTRL_MOD_OFFSET+PILC2_BRAM_CTRL_CTRLREG_OFFSET, 
-			PILC2_BRAM_CFG_EN_WRITE_BRAM);
+	WriteFPGA(PILC2_BRAM_CTRL_MOD_OFFSET+BRAM_CTRL_CTRLREG_OFFSET, 
+			BRAM_CFG_EN_WRITE_BRAM);
 }
 
 
@@ -176,17 +176,17 @@ void PiLC2BRAMControllerEnWBRAM(void){
 ******************************************************************************/
 void PiLC2BRAMControllerDisWBRAM(void){
 	
-	WriteFPGA(PILC2_BRAM_CTRL_MOD_OFFSET+PILC2_BRAM_CTRL_CTRLREG_OFFSET, 0x0);
+	WriteFPGA(PILC2_BRAM_CTRL_MOD_OFFSET+BRAM_CTRL_CTRLREG_OFFSET, 0x0);
 }
 
 
 void PiLC2BRAMControllerSetHalfFullThreshold(int threshold){
 	
-	WriteFPGA(PILC2_BRAM_CTRL_MOD_OFFSET+PILC2_BRAM_CTRL_H_FULL_THR_OFFSET, 
+	WriteFPGA(PILC2_BRAM_CTRL_MOD_OFFSET+BRAM_CTRL_H_FULL_THR_OFFSET, 
 			threshold);
 }
 void PiLC2BRAMControllerSetFullThreshold(int threshold){
-	WriteFPGA(PILC2_BRAM_CTRL_MOD_OFFSET+PILC2_BRAM_CTRL_FULL_THR_OFFSET, 
+	WriteFPGA(PILC2_BRAM_CTRL_MOD_OFFSET+BRAM_CTRL_FULL_THR_OFFSET, 
 			threshold);
 }
 
@@ -207,7 +207,7 @@ unsigned int PiLC2BRAMControllerGetStatus(void){
 	unsigned int value;
 	
 	value = ReadFPGA(PILC2_BRAM_CTRL_MOD_OFFSET+
-					PILC2_BRAM_CTRL_STATUS_REG_OFFSET);
+					BRAM_CTRL_STATUS_REG_OFFSET);
 	
 	return value;
 }

pilc2_functions/pilc2_bram_controller.h

@@ -10,19 +10,19 @@
 
 /************************** Constant Definitions *****************************/
 
-#define PILC2_BRAM_CTRL_MOD_OFFSET			(0x500>>2)
-
-#define PILC2_BRAM_CTRL_CTRLREG_OFFSET		0x0
-#define	PILC2_BRAM_CTRL_WCOUNT_OFFSET		0x1
-#define	PILC2_BRAM_CTRL_FIFO_COUNT_OFFSET	0x2
-#define	PILC2_BRAM_CTRL_H_FULL_THR_OFFSET	0x3
-#define	PILC2_BRAM_CTRL_FULL_THR_OFFSET		0x4
-#define	PILC2_BRAM_CTRL_STATUS_REG_OFFSET	0x5
-
-#define PILC2_BRAM_CFG_EN_WRITE_BRAM		0x1
-#define PILC2_BRAM_CFG_RESET_BRAM_CTR		0x2
-#define PILC2_BRAM_CFG_RESET_FIFO			0x4
-#define PILC2_BRAM_CFG_RESET_MODULE			0x6
+#define PILC2_BRAM_CTRL_MOD_OFFSET		(0x500>>2)
+
+#define BRAM_CTRL_CTRLREG_OFFSET		0x0
+#define	BRAM_CTRL_WCOUNT_OFFSET			0x1
+#define	BRAM_CTRL_FIFO_COUNT_OFFSET		0x2
+#define	BRAM_CTRL_H_FULL_THR_OFFSET		0x3
+#define	BRAM_CTRL_FULL_THR_OFFSET		0x4
+#define	BRAM_CTRL_STATUS_REG_OFFSET		0x5
+
+#define BRAM_CFG_EN_WRITE_BRAM		0x1
+#define BRAM_CFG_RESET_BRAM_CTR		0x2
+#define BRAM_CFG_RESET_FIFO			0x4
+#define BRAM_CFG_RESET_MODULE		0x6
 
 /************************** Function Prototypes ******************************/
 

pilc2_functions/pilc2_counter_module.c

@@ -29,7 +29,7 @@
 void PiLC2CounterEnableCounter(void){
 	
 	/* only set the counter enable bit */
-	WriteFPGA(PILC2_CTR_MOD_OFFSET+PILC2_CTR_MOD_CTRLREG_OFFSET, 1);
+	WriteFPGA(PILC2_CTR_OFFSET+CTR_CTRL_REG, 1);
 }
 
 
@@ -48,6 +48,6 @@ void PiLC2CounterEnableCounter(void){
 void PiLC2CounterDisableCounter(void){
 	
 	/* only reset the counter enable bit */
-	WriteFPGA(PILC2_CTR_MOD_OFFSET+PILC2_CTR_MOD_CTRLREG_OFFSET, 0);	
+	WriteFPGA(PILC2_CTR_OFFSET+CTR_CTRL_REG, 0);	
 }
 

pilc2_functions/pilc2_counter_module.h

@@ -3,37 +3,26 @@
 
 /************************** Constant Definitions *****************************/
 
-#define PILC2_CTR_MOD_OFFSET				(0x400>>2)
-
-#define PILC2_CTR_MOD_CTRLREG_OFFSET		0x0
-#define PILC2_CTR_MOD_INTGATECTR_OFFSET		0x1
-#define PILC2_CTR_MOD_NROFCTR_OFFSET		0x2
-#define PILC2_CTR_MOD_INTGATEDDS_OFFSET		0x3
-
-#define PILC2_CTR_CFG_INT_GATE				0x2
-#define PILC2_CTR_CFG_EXT_GATE				0x0
-
-#define PILC2_CTR_CFG_LOAD_GATE 			0x4
-
-#define PILC2_CTR_CFG_FREERUN_EN			0x8
-#define PILC2_CTR_CFG_FREERUN_DIS			0x0
-
-#define PILC2_CTR_COUNTER_0_OFFSET			0xA
-#define PILC2_CTR_COUNTER_1_OFFSET			0xB
-#define PILC2_CTR_COUNTER_2_OFFSET			0xC
-#define PILC2_CTR_COUNTER_3_OFFSET			0xD
-#define PILC2_CTR_COUNTER_4_OFFSET			0xE
-#define PILC2_CTR_COUNTER_5_OFFSET			0xF
-#define PILC2_CTR_COUNTER_6_OFFSET			0x10
-#define PILC2_CTR_COUNTER_7_OFFSET			0x11
-#define PILC2_CTR_COUNTER_8_OFFSET			0x12
-#define PILC2_CTR_COUNTER_9_OFFSET			0x13
-#define PILC2_CTR_COUNTER_10_OFFSET			0x14
-#define PILC2_CTR_COUNTER_11_OFFSET			0x15
-#define PILC2_CTR_COUNTER_12_OFFSET			0x16
-#define PILC2_CTR_COUNTER_13_OFFSET			0x17
-#define PILC2_CTR_GATE_COUNTER_OFFSET		0x18
-#define PILC2_CTR_EXP_COUNTER_OFFSET		0x19
+#define PILC2_CTR_OFFSET				(0x400>>2)
+
+#define CTR_CTRL_REG				0x0
+
+#define CTR_CH_0		0xA
+#define CTR_CH_1		0xB
+#define CTR_CH_2		0xC
+#define CTR_CH_3		0xD
+#define CTR_CH_4		0xE
+#define CTR_CH_5		0xF
+#define CTR_CH_6		0x10
+#define CTR_CH_7		0x11
+#define CTR_CH_8		0x12
+#define CTR_CH_9		0x13
+#define CTR_CH_10			0x14
+#define CTR_CH_11			0x15
+#define CTR_CH_12			0x16
+#define CTR_CH_13			0x17
+#define CTR_GATE_COUNTER	0x18
+#define CTR_EXP_COUNTER		0x19
 
 
 /************************** Function Prototypes ******************************/

pilc2_functions/pilc2_dac.h

@@ -10,22 +10,24 @@
 /*************************** Constant Definitions *****************************/
 
 #define PILC_DAC_OFFSET 	(0x4000>>2)
-#define PILC_DAC_CH_0		0x0
-#define PILC_DAC_CH_1		0x1
-#define PILC_DAC_CH_2		0x2
-#define PILC_DAC_CH_3		0x3
-#define PILC_DAC_CH_4		0x4
-#define PILC_DAC_CH_5		0x5
-#define PILC_DAC_CH_6		0x6
-#define PILC_DAC_CH_7		0x7
-#define PILC_DAC_CH_8		0x8
-#define PILC_DAC_CH_9		0x9
-#define PILC_DAC_CH_10		0xA
-#define PILC_DAC_CH_11		0xB
-#define PILC_DAC_CH_12		0xC
-#define PILC_DAC_CH_13		0xD
-#define PILC_DAC_CH_14		0xE
-#define PILC_DAC_CH_15		0xF
+#define DAC_CH_0		0x0
+#define DAC_CH_1		0x1
+#define DAC_CH_2		0x2
+#define DAC_CH_3		0x3
+#define DAC_CH_4		0x4
+#define DAC_CH_5		0x5
+#define DAC_CH_6		0x6
+#define DAC_CH_7		0x7
+#define DAC_CH_8		0x8
+#define DAC_CH_9		0x9
+#define DAC_CH_10		0xA
+#define DAC_CH_11		0xB
+#define DAC_CH_12		0xC
+#define DAC_CH_13		0xD
+#define DAC_CH_14		0xE
+#define DAC_CH_15		0xF
+
+#define DAC_INPUT_CFG	0x14		//w
 
 /*************************** Function Prototypes ******************************/
 

pilc2_functions/pilc2_dadc.c

@@ -23,7 +23,7 @@
 *
 *******************************************************************************/
 int getDADCvalue(char DADCchannel) {
-	int dadc_value = ReadFPGA(PILC_DADC_OFFSET+PILC_DADC_VAL_OFFSET+DADCchannel);
+	int dadc_value = ReadFPGA(PILC_DADC_OFFSET+DADC_DATA_OFFSET+DADCchannel);
 	
 	return dadc_value;
 }
@@ -42,7 +42,7 @@ int getDADCvalue(char DADCchannel) {
 *
 *******************************************************************************/
 int getDADCRawvalue(char DADCchannel) {
-	int dadc_value = ReadFPGA(PILC_DADC_OFFSET+PILC_DADC_RAW_OFFSET+DADCchannel);
+	int dadc_value = ReadFPGA(PILC_DADC_OFFSET+DADC_RAW_OFFSET+DADCchannel);
 	
 	return dadc_value;
 }

pilc2_functions/pilc2_dadc.h

@@ -9,16 +9,16 @@
 
 /*************************** Constant Definitions *****************************/
 #define PILC_DADC_OFFSET 		(0x5000>>2)
-#define PILC_DADC_VAL_OFFSET	0x10
-#define PILC_DADC_RAW_OFFSET	0x18
-#define PILC_DADC_CH_0			0x0
-#define PILC_DADC_CH_1			0x1
-#define PILC_DADC_CH_2			0x2
-#define PILC_DADC_CH_3			0x3
-#define PILC_DADC_CH_4			0x4
-#define PILC_DADC_CH_5			0x5
-#define PILC_DADC_CH_6			0x6
-#define PILC_DADC_CH_7			0x7
+#define DADC_DATA_OFFSET		0x10
+#define DADC_RAW_OFFSET			0x18
+#define DADC_CH_0			0x0
+#define DADC_CH_1			0x1
+#define DADC_CH_2			0x2
+#define DADC_CH_3			0x3
+#define DADC_CH_4			0x4
+#define DADC_CH_5			0x5
+#define DADC_CH_6			0x6
+#define DADC_CH_7			0x7
 
 /*************************** Function Prototypes ******************************/
 

pilc2_functions/pilc2_encoder.c

@@ -26,9 +26,9 @@
 *******************************************************************************/
 int EncoderLoadPreloadValue(unsigned int EncChannel) {
 	
-	WriteFPGA(PILC_ENCODER_OFFSET+PILC_ENCODER_LPRLVREG, EncChannel);
+	WriteFPGA(PILC_ENCODER_OFFSET+ENCODER_LPRLVREG, EncChannel);
 	
-	WriteFPGA(PILC_ENCODER_OFFSET+PILC_ENCODER_LPRLVREG, 0x0);
+	WriteFPGA(PILC_ENCODER_OFFSET+ENCODER_LPRLVREG, 0x0);
 	
 	return 0;
 }
@@ -47,7 +47,7 @@ int EncoderLoadPreloadValue(unsigned int EncChannel) {
 *******************************************************************************/
 int EncoderSetPreloadValue(unsigned int channel, unsigned int preload_value) {
 
-	WriteFPGA(PILC_ENCODER_OFFSET+PILC_ENCODER_PRLV_OFFSET+channel, preload_value);
+	WriteFPGA(PILC_ENCODER_OFFSET+ENCODER_PRLV_OFFSET+channel, preload_value);
 	
 	return 0;
 }
@@ -66,7 +66,7 @@ int EncoderSetPreloadValue(unsigned int channel, unsigned int preload_value) {
 int EncoderGetValue(unsigned int channel) {
 	unsigned int value;
 
-	value = ReadFPGA(PILC_ENCODER_OFFSET+PILC_ENCODER_VAL_OFFSET+channel);
+	value = ReadFPGA(PILC_ENCODER_OFFSET+ENCODER_VAL_OFFSET+channel);
 	
 	return value;
 }

pilc2_functions/pilc2_encoder.h

@@ -9,19 +9,21 @@
 
 /*************************** Constant Definitions *****************************/
 #define PILC_ENCODER_OFFSET		(0x9000>>2)
+#define ENCODER_PRLV_OFFSET		0x8
+#define ENCODER_VAL_OFFSET		0x10
 
-#define PILC_ENCODER_LPRLVREG		0x0
-#define PILC_ENCODER_PRLV_OFFSET	0x8
-#define PILC_ENCODER_VAL_OFFSET		0x10
 
-#define PILC_ENCODER_CH_0		0x0
-#define PILC_ENCODER_CH_1		0x1
-#define PILC_ENCODER_CH_2		0x2
-#define PILC_ENCODER_CH_3		0x3
-#define PILC_ENCODER_CH_4		0x4
-#define PILC_ENCODER_CH_5		0x5
-#define PILC_ENCODER_CH_6		0x6
-#define PILC_ENCODER_CH_7		0x7
+#define ENCODER_LPRLVREG		0x0
+
+
+#define ENCODER_CH_0		0x0
+#define ENCODER_CH_1		0x1
+#define ENCODER_CH_2		0x2
+#define ENCODER_CH_3		0x3
+#define ENCODER_CH_4		0x4
+#define ENCODER_CH_5		0x5
+#define ENCODER_CH_6		0x6
+#define ENCODER_CH_7		0x7
 
 /*************************** Function Prototypes ******************************/
 

pilc2_functions/pilc2_fifoser.c

@@ -29,7 +29,7 @@
 int setFifoSerCfg(unsigned int config)
 {
 	
-	WriteFPGA(PILC_FIFOSER_OFFSET+PILC_FIFOSER_CTRL_REG, config);
+	WriteFPGA(PILC_FIFOSER_OFFSET+FIFOSER_CTRL_REG, config);
 	
 	return 0;
 }
@@ -39,7 +39,7 @@ int setFifoSerCfg(unsigned int config)
 int setFifoSerChCfg(unsigned int channel, unsigned int config)
 {
 	
-	WriteFPGA(PILC_FIFOSER_OFFSET+PILC_FIFOSER_CH_OFFSET+channel, config);
+	WriteFPGA(PILC_FIFOSER_OFFSET+FIFOSER_CH_OFFSET+channel, config);
 	
 	return 0;
 }

pilc2_functions/pilc2_fifoser.h

@@ -11,25 +11,27 @@
 /*************************** Constant Definitions *****************************/
 
 #define PILC_FIFOSER_OFFSET 	(0xB000>>2)
-#define PILC_FIFOSER_CH_OFFSET	0xA
+#define FIFOSER_CH_OFFSET	0xA	
 
-#define PILC_FIFOSER_CTRL_REG	0x00
-#define PILC_FIFOSER_CFG_0		0x0
-#define PILC_FIFOSER_CFG_1		0x1
-#define PILC_FIFOSER_CFG_2		0x2
-#define PILC_FIFOSER_CFG_3		0x3
-#define PILC_FIFOSER_CFG_4		0x4
-#define PILC_FIFOSER_CFG_5		0x5
-#define PILC_FIFOSER_CFG_6		0x6
-#define PILC_FIFOSER_CFG_7		0x7
-#define PILC_FIFOSER_CFG_8		0x8
-#define PILC_FIFOSER_CFG_9		0x9
-#define PILC_FIFOSER_CFG_10		0xA
-#define PILC_FIFOSER_CFG_11		0xB
-#define PILC_FIFOSER_CFG_12		0xC
-#define PILC_FIFOSER_CFG_13		0xD
-#define PILC_FIFOSER_CFG_14		0xE
-#define PILC_FIFOSER_CFG_15		0xF
+#define FIFOSER_CTRL_REG	0x0
+#define FIFOSER_GATETHR		0x1			
+
+#define FIFOSER_CH_0		0x0
+#define FIFOSER_CH_1		0x1
+#define FIFOSER_CH_2		0x2
+#define FIFOSER_CH_3		0x3
+#define FIFOSER_CH_4		0x4
+#define FIFOSER_CH_5		0x5
+#define FIFOSER_CH_6		0x6
+#define FIFOSER_CH_7		0x7
+#define FIFOSER_CH_8		0x8
+#define FIFOSER_CH_9		0x9
+#define FIFOSER_CH_10		0xA
+