Commit bb749943 authored by Joshua Supra's avatar Joshua Supra
Browse files

changed address of logic module

parent ce8fad74
......@@ -56,7 +56,24 @@ int main (int argc, char *argv[]){
* */
IOMuxAutoConfig(IOCards);
/*setIOConfig(0, 0, IO_MUX_CFG_LOGIC, IOCARD_NIMTTL_TTL_IN);
setIOConfig(1, 0, IO_MUX_CFG_LOGIC, IOCARD_NIMTTL_TTL_IN);
setIOConfig(2, 0, IO_MUX_CFG_LOGIC, IOCARD_NIMTTL_TTL_IN);
setIOConfig(3, 1, IO_MUX_CFG_LOGIC, IOCARD_NIMTTL_TTL_OUT);
setIOConfig(4, 0, IO_MUX_CFG_LOGIC, IOCARD_NIMTTL_TTL_IN);
setIOConfig(5, 0, IO_MUX_CFG_LOGIC, IOCARD_NIMTTL_TTL_IN);
setIOConfig(6, 0, IO_MUX_CFG_LOGIC, IOCARD_NIMTTL_TTL_IN);
setIOConfig(7, 1, IO_MUX_CFG_LOGIC, IOCARD_NIMTTL_TTL_OUT);
setIOConfig(8, 0, IO_MUX_CFG_LOGIC, IOCARD_NIMTTL_TTL_IN);
setIOConfig(9, 0, IO_MUX_CFG_LOGIC, IOCARD_NIMTTL_TTL_IN);
setIOConfig(10, 0, IO_MUX_CFG_LOGIC, IOCARD_NIMTTL_TTL_IN);
setIOConfig(11, 1, IO_MUX_CFG_LOGIC, IOCARD_NIMTTL_TTL_OUT);
setIOConfig(12, 0, IO_MUX_CFG_LOGIC, IOCARD_NIMTTL_TTL_IN);
setIOConfig(13, 0, IO_MUX_CFG_LOGIC, IOCARD_NIMTTL_TTL_IN);
setIOConfig(14, 0, IO_MUX_CFG_LOGIC, IOCARD_NIMTTL_TTL_IN);
setIOConfig(15, 1, IO_MUX_CFG_LOGIC, IOCARD_NIMTTL_TTL_OUT); */
InitIOCards(IOCards);
zmq_recive_data[1] = malloc (sizeof(zmq_data));
......
......@@ -476,192 +476,3 @@ void getNIMTTLcolour(int card_slot, led_color_struct *led_color) {
}
}
/****************************************************************************/
/**
*
* Selfetest function for the inserted IO card.
*
*
* @param *IOCard is the pointer to the IOCardStruct array
*
* @return 0 on success
*
* @note None.
*
*****************************************************************************/
int SelftestIOCards (IOCardStruct *IOCard){
TestNIMTTLCard(IOCard);
return 0;
}
/****************************************************************************/
/**
*
* Selfetest function for NIM TTL IO cards. Ever slot will be checked for a
* NIM TTL IO card. When a card is present it will be set to each configuarion
* and the status register will be compared to the threshold. Afterwards the
* card will initialized to TTL input. A 500ms delay is inserted bewteen the
* different checks to avoid stressing the relay on the card and give the user
* the possibility to monitor the card behaviour.
*
*
* @param *IOCard is the pointer to the IOCardStruct array
*
* @return 0 on success
*
* @note None.
*
*****************************************************************************/
int TestNIMTTLCard (IOCardStruct *IOCard){
//set card status to TTL input
char card_status = IOCARD_NIMTTL_TTL_IN;
// process every card entry
for (int i = 0; i<15; i++) {
// check card entry for NIM TTL card
if (IOCard[i].TypeID == IOCARD_IS_NIMTTL) {
//set card status to TTL input
WriteFPGA(SPI_CS_MUX_OFFSET, i);
WriteIOCard(IOCARD_NIMTTL_WSTATUS, card_status);
//check every card for status: TTL input
if (card_status != ReadIOCard(IOCARD_IS_NIMTTL)) {
printf("error\n");
return -1;
}
}
}
// give relais on card some time to relax
usleep(500000);
// set card status to TTL output
card_status = IOCARD_NIMTTL_TTL_OUT;
for (int i = 0; i<15; i++) {
// check card entry for NIM TTL card
if (IOCard[i].TypeID == IOCARD_IS_NIMTTL) {
//set card status to TTL input
WriteFPGA(SPI_CS_MUX_OFFSET, i);
WriteIOCard(IOCARD_NIMTTL_WSTATUS, card_status);
//check every card for status: TTL input
if (card_status != ReadIOCard(IOCARD_IS_NIMTTL)) {
printf("error\n");
return -1;
}
}
}
// give relais on card some time to relax
usleep(500000);
// set card status to NIM input
card_status = IOCARD_NIMTTL_NIM_IN;
for (int i = 0; i<15; i++) {
// check card entry for NIM TTL card
if (IOCard[i].TypeID == IOCARD_IS_NIMTTL) {
//set card status to TTL input
WriteFPGA(SPI_CS_MUX_OFFSET, i);
WriteIOCard(IOCARD_NIMTTL_WSTATUS, card_status);
//check every card for status: TTL input
if (card_status != ReadIOCard(IOCARD_IS_NIMTTL)) {
printf("error\n");
return -1;
}
}
}
// give relais on card some time to relax
usleep(500000);
// set card status to NIM output
card_status = IOCARD_NIMTTL_NIM_OUT;
for (int i = 0; i<15; i++) {
// check card entry for NIM TTL card
if (IOCard[i].TypeID == IOCARD_IS_NIMTTL) {
//set card status to TTL input
WriteFPGA(SPI_CS_MUX_OFFSET, i);
WriteIOCard(IOCARD_NIMTTL_WSTATUS, card_status);
//check every card for status: TTL input
if (card_status != ReadIOCard(IOCARD_IS_NIMTTL)) {
printf("error\n");
return -1;
}
}
}
// give relais on card some time to relax
usleep(500000);
//set card status to TTL input
card_status = IOCARD_NIMTTL_TTL_IN;
// process every card entry
for (int i = 0; i<15; i++) {
// check card entry for NIM TTL card
if (IOCard[i].TypeID == IOCARD_IS_NIMTTL) {
//set card status to TTL input
WriteFPGA(SPI_CS_MUX_OFFSET, i);
WriteIOCard(IOCARD_NIMTTL_WSTATUS, card_status);
//check every card for status: TTL input
if (card_status != ReadIOCard(IOCARD_IS_NIMTTL)) {
printf("error\n");
return -1;
}
}
}
return 0;
}
#define PILC_LOGIC_OFFSET (0x10000>>2)
#define PILC_LOGIC_OFFSET (0xA000>>2)
#define PILC_LOGIC_CFG_OFFSET 0x0
#define PILC_LOGIC_DLY_OFFSET 0x4
......
......@@ -3,7 +3,7 @@
#define PILC_REG_START_ADDR 0x80000000
#define PILC_REG_END_ADDR 0x80010FFF
#define PILC_REG_END_ADDR 0x8000AFFF
#define PILC_REG_SIZE ( PILC_REG_END_ADDR - PILC_REG_START_ADDR )
......@@ -11,49 +11,6 @@
/**SPI CS mux**/
#define SPI_CS_MUX_OFFSET (0x200>>2) //0x100/4
#define IOR_Offset 0x4000
#define PIORO_0 IOR_Offset+0
#define PIORO_1 IOR_Offset+1
#define PIORO_2 IOR_Offset+2
#define PIORO_3 IOR_Offset+3
#define PIORO_4 IOR_Offset+4
#define PIORO_5 IOR_Offset+5
#define PIORO_6 IOR_Offset+6
#define PIORO_7 IOR_Offset+7
#define PIORO_8 IOR_Offset+8
#define PIORO_9 IOR_Offset+9
#define PIORO_10 IOR_Offset+10
#define PIORO_11 IOR_Offset+11
#define PIORO_12 IOR_Offset+12
#define PIORO_13 IOR_Offset+13
#define PIORO_14 IOR_Offset+14
#define PIORO_15 IOR_Offset+15
#define IORW_Offset IOR_Offset+0x1E
#define PIORW_0 IORW_Offset+0
#define PIORW_1 IORW_Offset+1
#define PIORW_2 IORW_Offset+2
#define PIORW_3 IORW_Offset+3
#define PIORW_4 IORW_Offset+4
#define PIORW_5 IORW_Offset+5
#define PIORW_6 IORW_Offset+6
#define PIORW_7 IORW_Offset+7
#define PIORW_8 IORW_Offset+8
#define PIORW_9 IORW_Offset+9
#define PIORW_10 IORW_Offset+10
#define PIORW_11 IORW_Offset+11
#define PIORW_12 IORW_Offset+12
#define PIORW_13 IORW_Offset+13
#define PIORW_14 IORW_Offset+14
#define PIORW_15 IORW_Offset+15
unsigned int *PiLC_Reg_base_addr;
unsigned int Reg_Space;
......
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