It was now agreed upon with the ChimeraTK team that mapfiles can use
dots as hierarchy separators in all cases (modules, regfiles, arrays of
memories). For VHDL code, an underscore is always used.

The code that creates strings for the template engine now always uses
the filetype-specific hierarchy separator to connect individual
sub-strings.

AXI4L ready valid signals on read channel were handled not properly. Only one
case was covered, ready before valid. In other cases external busses were not
working.

The 'IEEE754' option for fixedpoint breaks the indentation of generated
.map files

Adds support for the `Regfile` type of node, defined in SystemRDL 2.0,
as an internal instance. The register instances that it contains are
generated in VHDL similar to regular register instances. In mapfiles,
the instance name and index of the regfile is prepended to the name.

* multi-dimensional regfile instances are supported
* nested regfiles are not supported

When a DesyRDL-generated address space is integrated into a larger
design then it is probably not placed at address 0. The address decoder
should not use the full address from the bus interface, but only the
portion that it occupies itself. The upper bus structure is repsonsible
for only forwarding requests that are targeted at this instance.

Note that this is unlike PCI, for example, where each device on the bus
decodes the full address and "claims" the transaction for itself when it
is configured to decode that address.

PyPI doesn't support AsciiDoc for generating a project description from
the README.

The preferred way of defining the setup is by a static `setup.cfg`
file [1]. The build tools are defined in a `pyproject.toml`. This is
accordoing to PEP 517 and PEP 518.

[1] https://packaging.python.org/en/latest/tutorials/packaging-projects/

keep regwidth 2^n and provide information about used bits in register
needed for map file and VHDL

This fixes a bug introduced in 35f990e0.

The additional if condition prevented the logic from detecting a write
operation from the hardware if the software was reading simultaneously.

As a result, mcta4u_fw_programmer, by spamming reads to the WORD_CONTROL
register, prevented the status bit from being updated and gave up with a
timeout error.

There is no need to merge the outputs of the template engine for each
addrmap anymore. This option in DesyListener can now be removed.

Mapfiles and other formats like C header files must be created for a
complete register model at once, not for each individual `addrmap` node.

Use Python's subclasses and the reworked context generation to implement
a separate behavior for formats "vhdl" and "map".

BREAKING_CHANGE: top interfaces name change