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1.1.0
30094761
·
refactor: clock for AXI buses is from PL osc, add reset tree conf
·
Mar 18, 2024
1.0.0
b585676d
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fix: typo in FMC2 MGT port names for x5 chips
·
Feb 12, 2024
Release 1.0.0. Refactored and cleaned version for rev B and C