Skip to content
GitLab
Explore
Sign in
Open
4
Merged
48
Closed
9
All
61
Recent searches
Loading
{{ formattedKey }}
{{ title }}
{{ help }}
{{name}}
@{{username}}
None
Any
{{name}}
@{{username}}
None
Any
{{name}}
@{{username}}
None
Any
{{name}}
@{{username}}
{{name}}
@{{username}}
None
Any
Upcoming
Started
{{title}}
None
Any
{{title}}
None
Any
{{title}}
None
Any
{{name}}
Yes
No
Yes
No
{{title}}
{{title}}
{{title}}
Updated date
WIP: Generate register infrastructure from SystemRDL
!2
· created
Mar 10, 2021
by
Lukasz Butkowski
master
Closed
updated
Jun 14, 2024
refactor(ghdl): use analyze and elab, use gen depends to set file dependencies
!40
· created
Sep 26, 2023
by
Lukasz Butkowski
Closed
updated
Sep 27, 2023
FW and FWK Documenation (Epic #12259)
!39
· created
Sep 19, 2023
by
Lukasz Butkowski
Closed
2
updated
Sep 22, 2023
chore: update DesyRDL with multi-dim array fix
!23
· created
Sep 26, 2022
by
Lukasz Butkowski
Closed
1
updated
Oct 27, 2022
Draft: feat(addr): get list of DesyRDL files from .txt file
!14
· created
May 23, 2022
by
Lukasz Butkowski
Closed
1
updated
Oct 19, 2022
Support of underscore and real in VHDL config file parsing
!17
· created
Jul 08, 2022
by
Lukasz Butkowski
Closed
updated
Jul 08, 2022
Draft: Fwfwk sw
!12
· created
Apr 08, 2022
by
Lukasz Butkowski
Closed
updated
Apr 08, 2022
WIP: [addr] Call DesyRDL to generate mapfiles and VHDL
!8
· created
Jul 28, 2021
by
Lukasz Butkowski
desyrdl
Closed
updated
Oct 18, 2021
Makefile: Allow passing a TCLSH variable
!3
· created
Mar 17, 2021
by
Lukasz Butkowski
master
Closed
3
updated
May 19, 2021
