Explore projects

Generate VHDL and .map files from SystemRDL input

Main VHDL library

Data Acquisition Module that is used to sample signals and create AXI.4 Full packages (Manager).

Example project to test desyrdl with examples

Building blocks for the cooperative development of firmware and software.

BSP for the DAMC-FMC1Z7IO board

Decoder module for the timing information from timers.

mini-tlu, working as beam interface for CALICE AHCAL prototype

Application Module for DRTM-VM2HF and DRTM-VM2LF Rear Transition Modules

Motion Control project that will be used on PETRA IV photon beamlines. The target hardware is the DAMC-MOTCTRL board communicating with ZMX+ Phytron Motor Driver Card over optical links.