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A simplified version of the UNIO FMC board support package.

Example project for DRTM-AD84 rtm. By default with FMC1Z7IO BSP.

This is a clone of files prepared by DRS4 authors

Example project to test desyrdl with examples

Generate VHDL and .map files from SystemRDL input

Main VHDL library

Data Acquisition Module that is used to sample signals and create AXI.4 Full packages (Manager).

Example project for DAMC-FMC2ZUP card.

Building blocks for the cooperative development of firmware and software.

FPGAs of the wing-LDA in separate directory

Wing-LDA, all FPGAs and MARS module