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Uses xDMA implementation version of SIS8300KU BSP with quick start.

FPGAs of the wing-LDA in separate directory

Generate VHDL and .map files from SystemRDL input

CALICE AHCAL DIF2 firmware

Core library for the cooperative development of firmware & software, and the communication between them.

This is a clone of files prepared by DRS4 authors

Wing-LDA, all FPGAs and MARS module

Data Acquisition Module that is used to sample signals and create AXI.4 Full packages (Manager).