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Generate VHDL and .map files from SystemRDL input

Verification Projects for components under desy_vhdl library

Decoder module for the timing information from timers.

Generic Timing Module. Creates triggers, strobes for the application.

Building blocks for the cooperative development of firmware and software.

DRTM-DWC8VM1 rtm support package repo.

BSP module for SIS8300KU AMC board with xDMA implementation along with DesyRDL library

DRTM-DS8VM1 board support package.

BSP for DAMC-FMC2ZUP board

Application Module for DRTM-VM2HF and DRTM-VM2LF Rear Transition Modules

Application Module for DRTM-AD84 Rear Transition Module