Explore projects

Generate VHDL and .map files from SystemRDL input

The main firmware framework project

Example project to test desyrdl with examples

BSP for the DAMC-FMC1Z7IO board

Decoder module for the timing information from timers.

A simplified version of the UNIO FMC board support package.

Application Module for DRTM-VM2HF and DRTM-VM2LF Rear Transition Modules

DRTM-DWC8VM1 rtm support package repo.

DRTM-DS8VM1 board support package.

DRTM-PZT4 board support module

mini-tlu, working as beam interface for CALICE AHCAL prototype

FPGAs of the wing-LDA in separate directory