// File for Belle2 slow control access with PCIe40 

/* ---------------------------------------------------------------------- *\
   readfee8
   returns -1 in case of error
\* ---------------------------------------------------------------------- */
int pcie40_readfee8( int dev , int adr) {
  // PCIe40
  if ( ( adr <=0 ) || ( adr >= 0x7F ) ) return -1 ;
  // Reset the FIFO
  unsigned ret = 0 ;
  ret = ecs_write( dev , SLC_BAR , SLC_WFIFO_RESET_ADD , 1 << SLC_WFIFO_RESET_BIT ) ;
  if ( ret != 0 ) return -1 ;
  // Fill the FIFO with the requested information
  uint_64 data_word = 
    ( 0x73 ) | ( 0x07 << 8 ) | ( adr << 16 ) | ( 0x0c << 32 ) | ( 0x08 << 40 ) ;
  // (temporary : 32 bits only)
  ret = ecs_write( dev , SLC_BAR , SLC_WFIFO_ADD , (int) ( data_word & 0xFFFFFFFF ) ) ;
  if ( ret != 0 ) return -1 ;

  // Wait for the result to come back
  int i ;
  for ( i=0 ; i<10 ; i++ ) {
    usleep( 10 ) ; //10 ms
    ret = ecs_read( dev , SLC_BAR , SLC_RFIFO_STATUS ) ;
    if ( ret == 0x11 ) break;
  }

  if (i == 10) return -ETIME;

  // Read the value 
  ret = ecs_read( dev , SLC_BAR , SLC_RFIFO_ADD );

  return ret;
}