From f29943fab6f3759c13390fb721c755127e931d2f Mon Sep 17 00:00:00 2001
From: Patrick Robbe <robbe@lal.in2p3.fr>
Date: Tue, 11 Jun 2019 18:49:16 +0900
Subject: [PATCH] new structure
---
Pcie40Driver/pcie40_ioctl.h | 91 +++++++++++++++++++++++++++++++++++++
1 file changed, 91 insertions(+)
create mode 100644 Pcie40Driver/pcie40_ioctl.h
diff --git a/Pcie40Driver/pcie40_ioctl.h b/Pcie40Driver/pcie40_ioctl.h
new file mode 100644
index 0000000..80c4c6d
--- /dev/null
+++ b/Pcie40Driver/pcie40_ioctl.h
@@ -0,0 +1,91 @@
+#ifndef __PCIE40_IOCTL_H
+#define __PCIE40_IOCTL_H
+//ioctl.pcie``+
+
+#define P40_CTRL_GET_RWTEST _IOR('c', 1, uint64_t)//+`P40_CTRL_GET_RWTEST` ?>
+#define P40_CTRL_SET_RWTEST _IOW('c', 2, uint64_t)//+`P40_CTRL_SET_RWTEST` ?>
+#define P40_CTRL_GET_VERSION _IOR('c', 3, uint64_t)//+`P40_CTRL_GET_VERSION` ?>
+#define P40_CTRL_GET_LINK_ID _IOR('c', 4, uint64_t)//+`P40_CTRL_GET_LINK_ID` ?>
+#define P40_CTRL_GET_CHIP_ID _IOR('c', 5, uint64_t)//+`P40_CTRL_GET_CHIP_ID` ?>
+#define P40_CTRL_GET_ERROR _IOR('c', 6, uint64_t)//+`P40_CTRL_GET_ERROR` ?>
+#define P40_CTRL_GET_RESET _IOR('c', 7, uint64_t)//+`P40_CTRL_GET_RESET` ?>
+#define P40_CTRL_SET_RESET _IOW('c', 8, uint64_t)//+`P40_CTRL_SET_RESET` ?>
+#define P40_RST_BIT_DEFAULT (0)
+#define P40_RST_BIT_LOGIC (1)
+#define P40_RST_BIT_FLUSH (2)
+#define P40_RST_BIT_COUNTERS (3)
+#define P40_CTRL_GET_MAIN_GEN_CTL _IOR('c', 9, uint64_t)//+`P40_CTRL_GET_MAIN_GEN_CTL` ?>
+#define P40_CTRL_SET_MAIN_GEN_CTL _IOW('c', 10, uint64_t)//+`P40_CTRL_SET_MAIN_GEN_CTL` ?>
+#define P40_MAIN_GEN_BIT_ENABLE (0)
+#define P40_MAIN_GEN_BIT_RUNNING (1)
+#define P40_MAIN_GEN_BIT_FIXED (2)
+#define P40_MAIN_GEN_BIT_THROTTLE (3)
+#define P40_CTRL_GET_MAIN_GEN_FIXED _IOR('c', 11, uint64_t)//+`P40_CTRL_GET_MAIN_GEN_FIXED` ?>
+#define P40_CTRL_SET_MAIN_GEN_FIXED _IOW('c', 12, uint64_t)//+`P40_CTRL_SET_MAIN_GEN_FIXED` ?>
+#define P40_CTRL_GET_MAIN_RAW_MODE _IOR('c', 13, uint64_t)//+`P40_CTRL_GET_MAIN_RAW_MODE` ?>
+#define P40_CTRL_GET_PCIE_GEN _IOR('c', 14, uint64_t)//+`P40_CTRL_GET_PCIE_GEN` ?>
+#define P40_CTRL_GET_META_PACKING _IOR('c', 15, uint64_t)//+`P40_CTRL_GET_META_PACKING` ?>
+#define P40_CTRL_SET_META_PACKING _IOW('c', 16, uint64_t)//+`P40_CTRL_SET_META_PACKING` ?>
+#define P40_CTRL_GET_MSI_MODE _IOR('c', 17, uint64_t)//+`P40_CTRL_GET_MSI_MODE` ?>
+#define P40_CTRL_SET_MSI_MODE _IOW('c', 18, uint64_t)//+`P40_CTRL_SET_MSI_MODE` ?>
+#define P40_MSI_MODE_BIT_DAQ (0)
+#define P40_MSI_MODE_BIT_MAIN (1)
+#define P40_MSI_MODE_BIT_META (2)
+#define P40_CTRL_GET_MAIN_MSI_BYTES _IOR('c', 19, uint64_t)//+`P40_CTRL_GET_MAIN_MSI_BYTES` ?>
+#define P40_CTRL_SET_MAIN_MSI_BYTES _IOW('c', 20, uint64_t)//+`P40_CTRL_SET_MAIN_MSI_BYTES` ?>
+#define P40_CTRL_GET_MAIN_MSI_CYCLES _IOR('c', 21, uint64_t)//+`P40_CTRL_GET_MAIN_MSI_CYCLES` ?>
+#define P40_CTRL_GET_META_MSI_BYTES _IOR('c', 22, uint64_t)//+`P40_CTRL_GET_META_MSI_BYTES` ?>
+#define P40_CTRL_SET_META_MSI_BYTES _IOW('c', 23, uint64_t)//+`P40_CTRL_SET_META_MSI_BYTES` ?>
+#define P40_CTRL_GET_META_MSI_CYCLES _IOR('c', 24, uint64_t)//+`P40_CTRL_GET_META_MSI_CYCLES` ?>
+#define P40_CTRL_GET_META_MSI_BLOCKS _IOR('c', 25, uint64_t)//+`P40_CTRL_GET_META_MSI_BLOCKS` ?>
+#define P40_CTRL_SET_META_MSI_BLOCKS _IOW('c', 26, uint64_t)//+`P40_CTRL_SET_META_MSI_BLOCKS` ?>
+#define P40_CTRL_GET_INBUF_SIZE _IOR('c', 27, uint64_t)//+`P40_CTRL_GET_INBUF_SIZE` ?>
+#define P40_CTRL_GET_INBUF_FILL _IOR('c', 28, uint64_t)//+`P40_CTRL_GET_INBUF_FILL` ?>
+#define P40_CTRL_GET_TRUNC_THRES _IOR('c', 29, uint64_t)//+`P40_CTRL_GET_TRUNC_THRES` ?>
+#define P40_CTRL_SET_TRUNC_THRES _IOW('c', 30, uint64_t)//+`P40_CTRL_SET_TRUNC_THRES` ?>
+#define P40_CTRL_GET_TRUNC_TOTAL_CYCLES _IOR('c', 31, uint64_t)//+`P40_CTRL_GET_TRUNC_TOTAL_CYCLES` ?>
+#define P40_CTRL_GET_TRUNC_TOTAL_SINCE_EVID _IOR('c', 32, uint64_t)//+`P40_CTRL_GET_TRUNC_TOTAL_SINCE_EVID` ?>
+#define P40_CTRL_GET_TRUNC_LAST_CYCLES _IOR('c', 33, uint64_t)//+`P40_CTRL_GET_TRUNC_LAST_CYCLES` ?>
+#define P40_CTRL_GET_TRUNC_LAST_FROM_EVID _IOR('c', 34, uint64_t)//+`P40_CTRL_GET_TRUNC_LAST_FROM_EVID` ?>
+#define P40_CTRL_GET_TRUNC_LAST_TO_EVID _IOR('c', 35, uint64_t)//+`P40_CTRL_GET_TRUNC_LAST_TO_EVID` ?>
+#define P40_CTRL_GET_CHOKE_TOTAL_CYCLES _IOR('c', 36, uint64_t)//+`P40_CTRL_GET_CHOKE_TOTAL_CYCLES` ?>
+#define P40_CTRL_GET_CHOKE_TOTAL_SINCE_EVID _IOR('c', 37, uint64_t)//+`P40_CTRL_GET_CHOKE_TOTAL_SINCE_EVID` ?>
+#define P40_CTRL_GET_CHOKE_LAST_CYCLES _IOR('c', 38, uint64_t)//+`P40_CTRL_GET_CHOKE_LAST_CYCLES` ?>
+#define P40_CTRL_GET_CHOKE_LAST_FROM_EVID _IOR('c', 39, uint64_t)//+`P40_CTRL_GET_CHOKE_LAST_FROM_EVID` ?>
+#define P40_CTRL_GET_CHOKE_LAST_TO_EVID _IOR('c', 40, uint64_t)//+`P40_CTRL_GET_CHOKE_LAST_TO_EVID` ?>
+
+// this should advance both the main and meta read pointers
+// after parsing the metadata information
+// we might allow manually advancing the pointer,
+// but only in MSI_META and MSI_MAIN modes, never in MSI_DAQ
+#define P40_CTRL_GET_HOST_MAIN_MSI_NSECS _IOR('h', 2, uint64_t)//+`P40_CTRL_GET_HOST_MAIN_MSI_NSECS` ?>
+#define P40_CTRL_GET_HOST_META_MSI_NSECS _IOR('h', 3, uint64_t)//+`P40_CTRL_GET_HOST_META_MSI_NSECS` ?>
+
+#define P40_STREAM_GET_ENABLE _IOR('s', 1, uint64_t)//+`P40_STREAM_GET_ENABLE` ?>
+#define P40_STREAM_SET_ENABLE _IOW('s', 2, uint64_t)//+`P40_STREAM_SET_ENABLE` ?>
+#define P40_STREAM_GET_READY _IOR('s', 3, uint64_t)//+`P40_STREAM_GET_READY` ?>
+#define P40_STREAM_GET_FLUSH _IOR('s', 4, uint64_t)//+`P40_STREAM_GET_FLUSH` ?>
+#define P40_STREAM_SET_FLUSH _IOW('s', 5, uint64_t)//+`P40_STREAM_SET_FLUSH` ?>
+#define P40_STREAM_GET_FPGA_BUF_BYTES _IOR('s', 6, uint64_t)//+`P40_STREAM_GET_FPGA_BUF_BYTES` ?>
+#define P40_STREAM_GET_FPGA_BUF_DESCS _IOR('s', 7, uint64_t)//+`P40_STREAM_GET_FPGA_BUF_DESCS` ?>
+
+#define P40_STREAM_GET_FPGA_BUF_DESC_BYTES _IOR('s', 8, uint64_t)//+`P40_STREAM_GET_FPGA_BUF_DESC_BYTES` ?>
+
+#define P40_STREAM_GET_FPGA_BUF_DESCS_FILL _IOR('s', 9, uint64_t)//+`P40_STREAM_GET_FPGA_BUF_DESCS_FILL` ?>
+
+#define P40_STREAM_GET_FPGA_BUF_DESC_FILL_BYTES _IOR('s', 10, uint64_t)//+`P40_STREAM_GET_FPGA_BUF_DESC_FILL_BYTES` ?>
+
+#define P40_STREAM_GET_FPGA_BUF_DESCS_BUSY _IOR('s', 11, uint64_t)//+`P40_STREAM_GET_FPGA_BUF_DESCS_BUSY` ?>
+
+#define P40_STREAM_GET_HOST_BUF_WRITE_OFF _IOR('s', 12, uint64_t)//+`P40_STREAM_GET_HOST_BUF_WRITE_OFF` ?>
+#define P40_STREAM_GET_HOST_BUF_READ_OFF _IOR('s', 13, uint64_t)//+`P40_STREAM_GET_HOST_BUF_READ_OFF` ?>
+
+#define P40_STREAM_GET_HOST_BUF_BYTES _IOR('m', 1, uint64_t)//+`P40_STREAM_GET_HOST_BUF_BYTES` ?>
+#define P40_STREAM_GET_HOST_BUF_BYTES_USED _IOR('m', 2, uint64_t)//+`P40_STREAM_GET_HOST_BUF_BYTES_USED` ?>
+#define P40_STREAM_GET_HOST_MSI_COUNT _IOR('m', 3, uint64_t)//+`P40_STREAM_GET_HOST_MSI_COUNT` ?>
+#define P40_STREAM_FREE_HOST_BUF_BYTES _IOWR('m', 4, uint64_t)//+`P40_STREAM_FREE_HOST_BUF_BYTES` ?>
+
+#define P40_ECS_GET_BAR_SIZE _IO('e', 1) //+`P40_ECS_GET_BAR_SIZE` ?>
+//TODO: why not _IOR?
+
+#endif//__PCIE40_IOCTL_H
--
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