diff --git a/Python/data/Si5344-RevB-TFC_127-Registers.txt b/Python/data/Si5344-BII_FTSW-Registers.txt
similarity index 81%
rename from Python/data/Si5344-RevB-TFC_127-Registers.txt
rename to Python/data/Si5344-BII_FTSW-Registers.txt
index 6eb2a62ddbcbf5aa09de7dfe6b6c03878d36eb4f..be78f2b95a6eeba969755acfcf60310be54ca467 100644
--- a/Python/data/Si5344-RevB-TFC_127-Registers.txt
+++ b/Python/data/Si5344-BII_FTSW-Registers.txt
@@ -1,12 +1,12 @@
# Si538x/4x Registers Script
#
# Part: Si5344
-# Project File: C:\Users\belle2daq\Desktop\Si5344-RevB-Bell2-TFC_40-Project2.slabtimeproj
-# Design ID: TFC_40
+# Project File: D:\Work\Belle2 DAQ\pllsconfig\Si5344-BII_FTSW.slabtimeproj
+# Design ID: BII_FTSW
# Includes Pre/Post Download Control Register Writes: Yes
# Die Revision: A2
# Creator: ClockBuilder Pro v2.29 [2018-11-04]
-# Created On: 2018-11-29 11:30:10 GMT+01:00
+# Created On: 2019-01-29 12:31:40 GMT+01:00
Address,Data
#
# Start configuration preamble
@@ -30,7 +30,7 @@ Address,Data
0x002B,0x02
0x002C,0x01
0x002D,0x01
-0x002E,0x38
+0x002E,0x39
0x002F,0x00
0x0030,0x00
0x0031,0x00
@@ -38,7 +38,7 @@ Address,Data
0x0033,0x00
0x0034,0x00
0x0035,0x00
-0x0036,0x38
+0x0036,0x39
0x0037,0x00
0x0038,0x00
0x0039,0x00
@@ -53,22 +53,22 @@ Address,Data
0x0043,0x00
0x0044,0x00
0x0045,0x0C
-0x0046,0xFF
+0x0046,0x32
0x0047,0x00
0x0048,0x00
0x0049,0x00
-0x004A,0xFE
+0x004A,0x31
0x004B,0x00
0x004C,0x00
0x004D,0x00
0x004E,0x05
0x004F,0x00
0x0050,0x0F
-0x0051,0x0F
+0x0051,0x03
0x0052,0x00
0x0053,0x00
0x0054,0x00
-0x0055,0x0E
+0x0055,0x02
0x0056,0x00
0x0057,0x00
0x0058,0x00
@@ -100,8 +100,8 @@ Address,Data
0x009E,0x40
0x00A0,0x20
0x00A2,0x02
-0x00A8,0x79
-0x00A9,0x10
+0x00A8,0xD4
+0x00A9,0x6B
0x00AA,0x07
0x00AB,0x00
0x00AC,0x00
@@ -114,11 +114,11 @@ Address,Data
0x0118,0x09
0x0119,0x3D
0x011A,0x00
-0x0126,0x06
+0x0126,0x01
0x0127,0x09
0x0128,0x3D
0x0129,0x00
-0x012B,0x06
+0x012B,0x01
0x012C,0x09
0x012D,0x3D
0x012E,0x00
@@ -131,15 +131,15 @@ Address,Data
0x0204,0x00
0x0205,0x00
0x0206,0x00
-0x0208,0x2B
-0x0209,0xD7
-0x020A,0xCD
-0x020B,0x1F
+0x0208,0x40
+0x0209,0x00
+0x020A,0x00
+0x020B,0x00
0x020C,0x00
0x020D,0x00
-0x020E,0x00
+0x020E,0x01
0x020F,0x00
-0x0210,0x80
+0x0210,0x00
0x0211,0x00
0x0212,0x00
0x0213,0x00
@@ -171,20 +171,20 @@ Address,Data
0x022D,0x00
0x022E,0x00
0x022F,0x00
-0x0231,0x11
+0x0231,0x01
0x0232,0x01
0x0233,0x01
0x0234,0x01
0x0235,0x00
0x0236,0x00
-0x0237,0x00
-0x0238,0x80
-0x0239,0x7F
+0x0237,0x80
+0x0238,0xD2
+0x0239,0xAA
0x023A,0x00
0x023B,0x00
0x023C,0x00
-0x023D,0x00
-0x023E,0x80
+0x023D,0xC0
+0x023E,0xA8
0x0250,0x00
0x0251,0x00
0x0252,0x00
@@ -197,19 +197,19 @@ Address,Data
0x025F,0x00
0x0260,0x00
0x0261,0x00
-0x026B,0x54
-0x026C,0x46
-0x026D,0x43
+0x026B,0x42
+0x026C,0x49
+0x026D,0x49
0x026E,0x5F
-0x026F,0x34
-0x0270,0x30
-0x0271,0x00
-0x0272,0x00
+0x026F,0x46
+0x0270,0x54
+0x0271,0x53
+0x0272,0x57
0x0302,0x00
0x0303,0x00
0x0304,0x00
0x0305,0x80
-0x0306,0x0D
+0x0306,0x1B
0x0307,0x00
0x0308,0x00
0x0309,0x00
@@ -297,17 +297,17 @@ Address,Data
0x0512,0x07
0x0513,0x3F
0x0515,0x00
-0x0516,0x71
-0x0517,0x5B
-0x0518,0x80
-0x0519,0xB0
+0x0516,0x00
+0x0517,0x00
+0x0518,0x00
+0x0519,0xC0
0x051A,0x02
0x051B,0x00
0x051C,0x00
0x051D,0x00
0x051E,0x00
0x051F,0x80
-0x0521,0x31
+0x0521,0x21
0x052A,0x01
0x052B,0x01
0x052C,0x0F
@@ -315,7 +315,7 @@ Address,Data
0x052E,0x19
0x052F,0x19
0x0531,0x00
-0x0532,0x42
+0x0532,0x47
0x0533,0x03
0x0534,0x00
0x0535,0x00
@@ -334,7 +334,7 @@ Address,Data
0x0A03,0x01
0x0A04,0x01
0x0A05,0x01
-0x0B44,0x0E
+0x0B44,0x2F
0x0B46,0x00
0x0B47,0x0E
0x0B48,0x0E
diff --git a/Python/data/Si5344-BII_OSCI-Registers.txt b/Python/data/Si5344-BII_OSCI-Registers.txt
new file mode 100644
index 0000000000000000000000000000000000000000..b0eddd046a4cb7fe4214edbce8fb739e61bde72e
--- /dev/null
+++ b/Python/data/Si5344-BII_OSCI-Registers.txt
@@ -0,0 +1,350 @@
+# Si538x/4x Registers Script
+#
+# Part: Si5344
+# Project File: D:\Work\Belle2 DAQ\pllsconfig\Si5344-BII_OSCI.slabtimeproj
+# Design ID: BII_OSCI
+# Includes Pre/Post Download Control Register Writes: Yes
+# Die Revision: A2
+# Creator: ClockBuilder Pro v2.29 [2018-11-04]
+# Created On: 2019-01-29 12:36:30 GMT+01:00
+Address,Data
+#
+# Start configuration preamble
+0x0B24,0xD8
+0x0B25,0x00
+0x0540,0x01
+# End configuration preamble
+#
+# Delay 300 msec
+# Delay is worst case time for device to complete any calibration
+# that is running due to device state change previous to this script
+# being processed.
+#
+# Start configuration registers
+0x000B,0x68
+0x0016,0x02
+0x0017,0x1C
+0x0018,0xFF
+0x0019,0xFF
+0x001A,0xFF
+0x002B,0x02
+0x002C,0x00
+0x002D,0x00
+0x002E,0x00
+0x002F,0x00
+0x0030,0x00
+0x0031,0x00
+0x0032,0x00
+0x0033,0x00
+0x0034,0x00
+0x0035,0x00
+0x0036,0x00
+0x0037,0x00
+0x0038,0x00
+0x0039,0x00
+0x003A,0x00
+0x003B,0x00
+0x003C,0x00
+0x003D,0x00
+0x003F,0x00
+0x0040,0x04
+0x0041,0x00
+0x0042,0x00
+0x0043,0x00
+0x0044,0x00
+0x0045,0x0C
+0x0046,0x00
+0x0047,0x00
+0x0048,0x00
+0x0049,0x00
+0x004A,0x00
+0x004B,0x00
+0x004C,0x00
+0x004D,0x00
+0x004E,0x00
+0x004F,0x00
+0x0050,0x0F
+0x0051,0x00
+0x0052,0x00
+0x0053,0x00
+0x0054,0x00
+0x0055,0x00
+0x0056,0x00
+0x0057,0x00
+0x0058,0x00
+0x0059,0x00
+0x005A,0x00
+0x005B,0x00
+0x005C,0x00
+0x005D,0x00
+0x005E,0x00
+0x005F,0x00
+0x0060,0x00
+0x0061,0x00
+0x0062,0x00
+0x0063,0x00
+0x0064,0x00
+0x0065,0x00
+0x0066,0x00
+0x0067,0x00
+0x0068,0x00
+0x0069,0x00
+0x0092,0x00
+0x0093,0x00
+0x0095,0x00
+0x0096,0x00
+0x0098,0x00
+0x009A,0x00
+0x009B,0x00
+0x009D,0x00
+0x009E,0x00
+0x00A0,0x00
+0x00A2,0x00
+0x00A8,0x00
+0x00A9,0x00
+0x00AA,0x00
+0x00AB,0x00
+0x00AC,0x00
+0x0102,0x01
+0x0112,0x06
+0x0113,0x09
+0x0114,0x3D
+0x0115,0x00
+0x0117,0x06
+0x0118,0x09
+0x0119,0x3D
+0x011A,0x00
+0x0126,0x01
+0x0127,0x09
+0x0128,0x3D
+0x0129,0x00
+0x012B,0x01
+0x012C,0x09
+0x012D,0x3D
+0x012E,0x00
+0x013F,0x00
+0x0140,0x00
+0x0141,0x40
+0x0142,0xFF
+0x0202,0x00
+0x0203,0x00
+0x0204,0x00
+0x0205,0x00
+0x0206,0x00
+0x0208,0x00
+0x0209,0x00
+0x020A,0x00
+0x020B,0x00
+0x020C,0x00
+0x020D,0x00
+0x020E,0x00
+0x020F,0x00
+0x0210,0x00
+0x0211,0x00
+0x0212,0x00
+0x0213,0x00
+0x0214,0x00
+0x0215,0x00
+0x0216,0x00
+0x0217,0x00
+0x0218,0x00
+0x0219,0x00
+0x021A,0x00
+0x021B,0x00
+0x021C,0x00
+0x021D,0x00
+0x021E,0x00
+0x021F,0x00
+0x0220,0x00
+0x0221,0x00
+0x0222,0x00
+0x0223,0x00
+0x0224,0x00
+0x0225,0x00
+0x0226,0x00
+0x0227,0x00
+0x0228,0x00
+0x0229,0x00
+0x022A,0x00
+0x022B,0x00
+0x022C,0x00
+0x022D,0x00
+0x022E,0x00
+0x022F,0x00
+0x0231,0x01
+0x0232,0x01
+0x0233,0x01
+0x0234,0x01
+0x0235,0x00
+0x0236,0x00
+0x0237,0x00
+0x0238,0x78
+0x0239,0xF8
+0x023A,0x00
+0x023B,0x00
+0x023C,0x00
+0x023D,0x00
+0x023E,0xFA
+0x0250,0x00
+0x0251,0x00
+0x0252,0x00
+0x0253,0x00
+0x0254,0x00
+0x0255,0x00
+0x025C,0x00
+0x025D,0x00
+0x025E,0x00
+0x025F,0x00
+0x0260,0x00
+0x0261,0x00
+0x026B,0x42
+0x026C,0x49
+0x026D,0x49
+0x026E,0x5F
+0x026F,0x4F
+0x0270,0x53
+0x0271,0x43
+0x0272,0x49
+0x0302,0x00
+0x0303,0x00
+0x0304,0x00
+0x0305,0x00
+0x0306,0x1B
+0x0307,0x00
+0x0308,0x00
+0x0309,0x00
+0x030A,0x00
+0x030B,0x80
+0x030C,0x00
+0x030D,0x00
+0x030E,0x00
+0x030F,0x00
+0x0310,0x00
+0x0311,0x00
+0x0312,0x00
+0x0313,0x00
+0x0314,0x00
+0x0315,0x00
+0x0316,0x00
+0x0317,0x00
+0x0318,0x00
+0x0319,0x00
+0x031A,0x00
+0x031B,0x00
+0x031C,0x00
+0x031D,0x00
+0x031E,0x00
+0x031F,0x00
+0x0320,0x00
+0x0321,0x00
+0x0322,0x00
+0x0323,0x00
+0x0324,0x00
+0x0325,0x00
+0x0326,0x00
+0x0327,0x00
+0x0328,0x00
+0x0329,0x00
+0x032A,0x00
+0x032B,0x00
+0x032C,0x00
+0x032D,0x00
+0x0338,0x00
+0x0339,0x1F
+0x033B,0x00
+0x033C,0x00
+0x033D,0x00
+0x033E,0x00
+0x033F,0x00
+0x0340,0x00
+0x0341,0x00
+0x0342,0x00
+0x0343,0x00
+0x0344,0x00
+0x0345,0x00
+0x0346,0x00
+0x0347,0x00
+0x0348,0x00
+0x0349,0x00
+0x034A,0x00
+0x034B,0x00
+0x034C,0x00
+0x034D,0x00
+0x034E,0x00
+0x034F,0x00
+0x0350,0x00
+0x0351,0x00
+0x0352,0x00
+0x0359,0x00
+0x035A,0x00
+0x035B,0x00
+0x035C,0x00
+0x035D,0x00
+0x035E,0x00
+0x035F,0x00
+0x0360,0x00
+0x0487,0x00
+0x0508,0x00
+0x0509,0x00
+0x050A,0x00
+0x050B,0x00
+0x050C,0x00
+0x050D,0x00
+0x050E,0x00
+0x050F,0x00
+0x0510,0x00
+0x0511,0x00
+0x0512,0x00
+0x0513,0x00
+0x0515,0x00
+0x0516,0x00
+0x0517,0x00
+0x0518,0x00
+0x0519,0x00
+0x051A,0x00
+0x051B,0x00
+0x051C,0x00
+0x051D,0x00
+0x051E,0x00
+0x051F,0x00
+0x0521,0x21
+0x052A,0x01
+0x052B,0x01
+0x052C,0x0F
+0x052D,0x03
+0x052E,0x00
+0x052F,0x00
+0x0531,0x00
+0x0532,0x00
+0x0533,0x04
+0x0534,0x00
+0x0535,0x01
+0x0536,0x0C
+0x0537,0x00
+0x0538,0x00
+0x0539,0x00
+0x0802,0x35
+0x0803,0x05
+0x0804,0x01
+0x090E,0x02
+0x0943,0x00
+0x0949,0x00
+0x094A,0x00
+0x0A02,0x00
+0x0A03,0x01
+0x0A04,0x01
+0x0A05,0x01
+0x0B44,0x0F
+0x0B46,0x00
+0x0B47,0x0F
+0x0B48,0x0F
+0x0B4A,0x0E
+# End configuration registers
+#
+# Start configuration postamble
+0x0514,0x01
+0x001C,0x01
+0x0540,0x00
+0x0B24,0xDB
+0x0B25,0x02
+# End configuration postamble
diff --git a/Python/data/Si5345-RevB-JIT1_255-JIT1_240_jitter1_input1_255MHz_new-Registers.txt b/Python/data/Si5345-1-BII_FPGA-Registers.txt
old mode 100755
new mode 100644
similarity index 80%
rename from Python/data/Si5345-RevB-JIT1_255-JIT1_240_jitter1_input1_255MHz_new-Registers.txt
rename to Python/data/Si5345-1-BII_FPGA-Registers.txt
index 2bfda095b86bff5a6e2dca454001744559b9ba92..eaaaf78ae59a84f2a8d0073b9b3c4fe463ee639e
--- a/Python/data/Si5345-RevB-JIT1_255-JIT1_240_jitter1_input1_255MHz_new-Registers.txt
+++ b/Python/data/Si5345-1-BII_FPGA-Registers.txt
@@ -1,12 +1,12 @@
# Si538x/4x Registers Script
#
# Part: Si5345
-# Project File: C:\Users\belle2daq\Desktop\Si5345-RevB-JIT1_255-Project_jitter1_input1_255MHz_mod_EP.slabtimeproj
-# Design ID: JIT1_240
+# Project File: D:\Work\Belle2 DAQ\pllsconfig\Si5345-1-BII_FPGA.slabtimeproj
+# Design ID: BII_FPGA
# Includes Pre/Post Download Control Register Writes: Yes
# Die Revision: A2
# Creator: ClockBuilder Pro v2.29 [2018-11-04]
-# Created On: 2019-01-23 10:56:43 GMT+01:00
+# Created On: 2019-01-29 14:13:22 GMT+01:00
Address,Data
#
# Start configuration preamble
@@ -32,7 +32,7 @@ Address,Data
0x002D,0x04
0x002E,0x00
0x002F,0x00
-0x0030,0xB7
+0x0030,0x3B
0x0031,0x00
0x0032,0x00
0x0033,0x00
@@ -40,7 +40,7 @@ Address,Data
0x0035,0x00
0x0036,0x00
0x0037,0x00
-0x0038,0xB7
+0x0038,0x3B
0x0039,0x00
0x003A,0x00
0x003B,0x00
@@ -49,7 +49,7 @@ Address,Data
0x003F,0x22
0x0040,0x04
0x0041,0x00
-0x0042,0x0E
+0x0042,0x0D
0x0043,0x00
0x0044,0x00
0x0045,0x0C
@@ -77,9 +77,9 @@ Address,Data
0x005B,0x00
0x005C,0x00
0x005D,0x00
-0x005E,0xE3
-0x005F,0x38
-0x0060,0x2E
+0x005E,0x8D
+0x005F,0x8C
+0x0060,0x2D
0x0061,0x01
0x0062,0x00
0x0063,0x00
@@ -100,9 +100,9 @@ Address,Data
0x009E,0x40
0x00A0,0x20
0x00A2,0x02
-0x00A8,0x4A
-0x00A9,0xEE
-0x00AA,0x15
+0x00A8,0x7F
+0x00A9,0xD8
+0x00AA,0x0F
0x00AB,0x00
0x00AC,0x00
0x0102,0x01
@@ -122,7 +122,7 @@ Address,Data
0x0118,0x09
0x0119,0x3D
0x011A,0x00
-0x011C,0x06
+0x011C,0x02
0x011D,0x09
0x011E,0x3D
0x011F,0x00
@@ -165,8 +165,8 @@ Address,Data
0x020F,0x00
0x0210,0x00
0x0211,0x00
-0x0212,0xA9
-0x0213,0x01
+0x0212,0x41
+0x0213,0x00
0x0214,0x00
0x0215,0x00
0x0216,0x00
@@ -202,26 +202,26 @@ Address,Data
0x0235,0x00
0x0236,0x00
0x0237,0x00
-0x0238,0x00
-0x0239,0x7F
+0x0238,0x69
+0x0239,0xD9
0x023A,0x00
0x023B,0x00
0x023C,0x00
-0x023D,0x00
-0x023E,0x80
-0x024A,0x01
+0x023D,0xF0
+0x023E,0xD2
+0x024A,0x03
0x024B,0x00
0x024C,0x00
-0x024D,0x01
+0x024D,0x03
0x024E,0x00
0x024F,0x00
-0x0250,0x01
+0x0250,0x03
0x0251,0x00
0x0252,0x00
-0x0253,0x7F
-0x0254,0x84
-0x0255,0x1E
-0x0256,0x00
+0x0253,0x03
+0x0254,0x00
+0x0255,0x00
+0x0256,0x01
0x0257,0x00
0x0258,0x00
0x0259,0x00
@@ -239,19 +239,19 @@ Address,Data
0x0268,0x00
0x0269,0x00
0x026A,0x00
-0x026B,0x4A
+0x026B,0x42
0x026C,0x49
-0x026D,0x54
-0x026E,0x31
-0x026F,0x5F
-0x0270,0x32
-0x0271,0x34
-0x0272,0x30
+0x026D,0x49
+0x026E,0x5F
+0x026F,0x46
+0x0270,0x50
+0x0271,0x47
+0x0272,0x41
0x0302,0x00
0x0303,0x00
0x0304,0x00
-0x0305,0x80
-0x0306,0x0D
+0x0305,0x00
+0x0306,0x07
0x0307,0x00
0x0308,0x00
0x0309,0x00
@@ -345,23 +345,23 @@ Address,Data
0x0362,0x00
0x0487,0x00
0x0508,0x14
-0x0509,0x21
-0x050A,0x0E
-0x050B,0x0D
-0x050C,0x03
+0x0509,0x22
+0x050A,0x0D
+0x050B,0x0C
+0x050C,0x01
0x050D,0x3F
-0x050E,0x19
-0x050F,0x2D
+0x050E,0x18
+0x050F,0x2C
0x0510,0x09
0x0511,0x08
-0x0512,0x03
+0x0512,0x01
0x0513,0x3F
0x0515,0x00
0x0516,0x00
0x0517,0x00
0x0518,0x00
-0x0519,0xEE
-0x051A,0x08
+0x0519,0xD8
+0x051A,0x02
0x051B,0x00
0x051C,0x00
0x051D,0x00
@@ -375,8 +375,8 @@ Address,Data
0x052E,0x19
0x052F,0x19
0x0531,0x00
-0x0532,0xDA
-0x0533,0x0A
+0x0532,0x54
+0x0533,0x03
0x0534,0x00
0x0535,0x00
0x0536,0x0C
diff --git a/Python/data/Si5345-1-BII_FTSW-Registers.txt b/Python/data/Si5345-1-BII_FTSW-Registers.txt
new file mode 100644
index 0000000000000000000000000000000000000000..d7ae205a3770a72bba6e752a6abace8888310a87
--- /dev/null
+++ b/Python/data/Si5345-1-BII_FTSW-Registers.txt
@@ -0,0 +1,410 @@
+# Si538x/4x Registers Script
+#
+# Part: Si5345
+# Project File: D:\Work\Belle2 DAQ\pllsconfig\Si5345-1-BII_FTSW.slabtimeproj
+# Design ID: BII_FTSW
+# Includes Pre/Post Download Control Register Writes: Yes
+# Die Revision: A2
+# Creator: ClockBuilder Pro v2.29 [2018-11-04]
+# Created On: 2019-01-29 14:13:47 GMT+01:00
+Address,Data
+#
+# Start configuration preamble
+0x0B24,0xD8
+0x0B25,0x00
+0x0540,0x01
+# End configuration preamble
+#
+# Delay 300 msec
+# Delay is worst case time for device to complete any calibration
+# that is running due to device state change previous to this script
+# being processed.
+#
+# Start configuration registers
+0x000B,0x68
+0x0016,0x02
+0x0017,0x1C
+0x0018,0xEE
+0x0019,0xDD
+0x001A,0xDF
+0x002B,0x02
+0x002C,0x01
+0x002D,0x01
+0x002E,0x3B
+0x002F,0x00
+0x0030,0x00
+0x0031,0x00
+0x0032,0x00
+0x0033,0x00
+0x0034,0x00
+0x0035,0x00
+0x0036,0x3B
+0x0037,0x00
+0x0038,0x00
+0x0039,0x00
+0x003A,0x00
+0x003B,0x00
+0x003C,0x00
+0x003D,0x00
+0x003F,0x11
+0x0040,0x04
+0x0041,0x0D
+0x0042,0x00
+0x0043,0x00
+0x0044,0x00
+0x0045,0x0C
+0x0046,0x32
+0x0047,0x00
+0x0048,0x00
+0x0049,0x00
+0x004A,0x31
+0x004B,0x00
+0x004C,0x00
+0x004D,0x00
+0x004E,0x05
+0x004F,0x00
+0x0050,0x0F
+0x0051,0x03
+0x0052,0x00
+0x0053,0x00
+0x0054,0x00
+0x0055,0x02
+0x0056,0x00
+0x0057,0x00
+0x0058,0x00
+0x0059,0x03
+0x005A,0x8D
+0x005B,0x8C
+0x005C,0x2D
+0x005D,0x01
+0x005E,0x00
+0x005F,0x00
+0x0060,0x00
+0x0061,0x00
+0x0062,0x00
+0x0063,0x00
+0x0064,0x00
+0x0065,0x00
+0x0066,0x00
+0x0067,0x00
+0x0068,0x00
+0x0069,0x00
+0x0092,0x00
+0x0093,0x00
+0x0095,0x00
+0x0096,0x00
+0x0098,0x00
+0x009A,0x02
+0x009B,0x20
+0x009D,0x00
+0x009E,0x40
+0x00A0,0x20
+0x00A2,0x02
+0x00A8,0x7F
+0x00A9,0xD8
+0x00AA,0x0F
+0x00AB,0x00
+0x00AC,0x00
+0x0102,0x01
+0x0108,0x02
+0x0109,0x09
+0x010A,0x3D
+0x010B,0x00
+0x010D,0x02
+0x010E,0x09
+0x010F,0x3D
+0x0110,0x00
+0x0112,0x02
+0x0113,0x09
+0x0114,0x3D
+0x0115,0x00
+0x0117,0x02
+0x0118,0x09
+0x0119,0x3D
+0x011A,0x00
+0x011C,0x02
+0x011D,0x09
+0x011E,0x3D
+0x011F,0x00
+0x0121,0x01
+0x0122,0x09
+0x0123,0x3B
+0x0124,0x00
+0x0126,0x01
+0x0127,0x09
+0x0128,0x3B
+0x0129,0x00
+0x012B,0x01
+0x012C,0x09
+0x012D,0x3B
+0x012E,0x00
+0x0130,0x01
+0x0131,0x09
+0x0132,0x3B
+0x0133,0x00
+0x013A,0x01
+0x013B,0x09
+0x013C,0x3B
+0x013D,0x00
+0x013F,0x00
+0x0140,0x00
+0x0141,0x40
+0x0142,0xFF
+0x0202,0x00
+0x0203,0x00
+0x0204,0x00
+0x0205,0x00
+0x0206,0x00
+0x0208,0x41
+0x0209,0x00
+0x020A,0x00
+0x020B,0x00
+0x020C,0x00
+0x020D,0x00
+0x020E,0x01
+0x020F,0x00
+0x0210,0x00
+0x0211,0x00
+0x0212,0x00
+0x0213,0x00
+0x0214,0x00
+0x0215,0x00
+0x0216,0x00
+0x0217,0x00
+0x0218,0x00
+0x0219,0x00
+0x021A,0x00
+0x021B,0x00
+0x021C,0x00
+0x021D,0x00
+0x021E,0x00
+0x021F,0x00
+0x0220,0x00
+0x0221,0x00
+0x0222,0x00
+0x0223,0x00
+0x0224,0x00
+0x0225,0x00
+0x0226,0x00
+0x0227,0x00
+0x0228,0x00
+0x0229,0x00
+0x022A,0x00
+0x022B,0x00
+0x022C,0x00
+0x022D,0x00
+0x022E,0x00
+0x022F,0x00
+0x0231,0x01
+0x0232,0x01
+0x0233,0x01
+0x0234,0x01
+0x0235,0x00
+0x0236,0x00
+0x0237,0x00
+0x0238,0x69
+0x0239,0xD9
+0x023A,0x00
+0x023B,0x00
+0x023C,0x00
+0x023D,0xF0
+0x023E,0xD2
+0x024A,0x03
+0x024B,0x00
+0x024C,0x00
+0x024D,0x03
+0x024E,0x00
+0x024F,0x00
+0x0250,0x03
+0x0251,0x00
+0x0252,0x00
+0x0253,0x03
+0x0254,0x00
+0x0255,0x00
+0x0256,0x01
+0x0257,0x00
+0x0258,0x00
+0x0259,0x00
+0x025A,0x00
+0x025B,0x00
+0x025C,0x00
+0x025D,0x00
+0x025E,0x00
+0x025F,0x00
+0x0260,0x00
+0x0261,0x00
+0x0262,0x00
+0x0263,0x00
+0x0264,0x00
+0x0268,0x00
+0x0269,0x00
+0x026A,0x00
+0x026B,0x42
+0x026C,0x49
+0x026D,0x49
+0x026E,0x5F
+0x026F,0x46
+0x0270,0x54
+0x0271,0x53
+0x0272,0x57
+0x0302,0x00
+0x0303,0x00
+0x0304,0x00
+0x0305,0x00
+0x0306,0x07
+0x0307,0x00
+0x0308,0x00
+0x0309,0x00
+0x030A,0x00
+0x030B,0x80
+0x030C,0x00
+0x030D,0x00
+0x030E,0x00
+0x030F,0x00
+0x0310,0x00
+0x0311,0x00
+0x0312,0x00
+0x0313,0x00
+0x0314,0x00
+0x0315,0x00
+0x0316,0x00
+0x0317,0x00
+0x0318,0x00
+0x0319,0x00
+0x031A,0x00
+0x031B,0x00
+0x031C,0x00
+0x031D,0x00
+0x031E,0x00
+0x031F,0x00
+0x0320,0x00
+0x0321,0x00
+0x0322,0x00
+0x0323,0x00
+0x0324,0x00
+0x0325,0x00
+0x0326,0x00
+0x0327,0x00
+0x0328,0x00
+0x0329,0x00
+0x032A,0x00
+0x032B,0x00
+0x032C,0x00
+0x032D,0x00
+0x032E,0x00
+0x032F,0x00
+0x0330,0x00
+0x0331,0x00
+0x0332,0x00
+0x0333,0x00
+0x0334,0x00
+0x0335,0x00
+0x0336,0x00
+0x0337,0x00
+0x0338,0x00
+0x0339,0x1F
+0x033B,0x00
+0x033C,0x00
+0x033D,0x00
+0x033E,0x00
+0x033F,0x00
+0x0340,0x00
+0x0341,0x00
+0x0342,0x00
+0x0343,0x00
+0x0344,0x00
+0x0345,0x00
+0x0346,0x00
+0x0347,0x00
+0x0348,0x00
+0x0349,0x00
+0x034A,0x00
+0x034B,0x00
+0x034C,0x00
+0x034D,0x00
+0x034E,0x00
+0x034F,0x00
+0x0350,0x00
+0x0351,0x00
+0x0352,0x00
+0x0353,0x00
+0x0354,0x00
+0x0355,0x00
+0x0356,0x00
+0x0357,0x00
+0x0358,0x00
+0x0359,0x00
+0x035A,0x00
+0x035B,0x00
+0x035C,0x00
+0x035D,0x00
+0x035E,0x00
+0x035F,0x00
+0x0360,0x00
+0x0361,0x00
+0x0362,0x00
+0x0487,0x00
+0x0508,0x14
+0x0509,0x22
+0x050A,0x0D
+0x050B,0x0C
+0x050C,0x01
+0x050D,0x3F
+0x050E,0x18
+0x050F,0x2C
+0x0510,0x09
+0x0511,0x08
+0x0512,0x01
+0x0513,0x3F
+0x0515,0x00
+0x0516,0x00
+0x0517,0x00
+0x0518,0x00
+0x0519,0xD8
+0x051A,0x02
+0x051B,0x00
+0x051C,0x00
+0x051D,0x00
+0x051E,0x00
+0x051F,0x80
+0x0521,0x21
+0x052A,0x01
+0x052B,0x01
+0x052C,0x0F
+0x052D,0x03
+0x052E,0x19
+0x052F,0x19
+0x0531,0x00
+0x0532,0x54
+0x0533,0x03
+0x0534,0x00
+0x0535,0x00
+0x0536,0x0C
+0x0537,0x00
+0x0538,0x00
+0x0539,0x00
+0x0802,0x35
+0x0803,0x05
+0x0804,0x00
+0x090E,0x02
+0x0943,0x00
+0x0949,0x01
+0x094A,0x01
+0x0A02,0x00
+0x0A03,0x01
+0x0A04,0x01
+0x0A05,0x01
+0x0B44,0x2F
+0x0B46,0x00
+0x0B47,0x0E
+0x0B48,0x0E
+0x0B4A,0x1E
+# End configuration registers
+#
+# Start configuration postamble
+0x0514,0x01
+0x001C,0x01
+0x0540,0x00
+0x0B24,0xDB
+0x0B25,0x02
+# End configuration postamble
diff --git a/Python/data/Si5345-RevB-JIT2_255-JIT2_240_jitter2_input1_255MHz_new-Registers.txt b/Python/data/Si5345-2-BII_FPGA-Registers.txt
old mode 100755
new mode 100644
similarity index 80%
rename from Python/data/Si5345-RevB-JIT2_255-JIT2_240_jitter2_input1_255MHz_new-Registers.txt
rename to Python/data/Si5345-2-BII_FPGA-Registers.txt
index d9355e41eebde0d0700e84874e2f6ad9974b4070..498446764b588921ad80689c85ca865ad9830072
--- a/Python/data/Si5345-RevB-JIT2_255-JIT2_240_jitter2_input1_255MHz_new-Registers.txt
+++ b/Python/data/Si5345-2-BII_FPGA-Registers.txt
@@ -1,12 +1,12 @@
# Si538x/4x Registers Script
#
# Part: Si5345
-# Project File: C:\Users\belle2daq\Desktop\Si5345-RevB-JIT2_255-JIT2_240-Project_jitter2_input1_255MHz_mod_EP.slabtimeproj
-# Design ID: JIT2_240
+# Project File: D:\Work\Belle2 DAQ\pllsconfig\Si5345-2-BII_FPGA.slabtimeproj
+# Design ID: BII_FPGA
# Includes Pre/Post Download Control Register Writes: Yes
# Die Revision: A2
# Creator: ClockBuilder Pro v2.29 [2018-11-04]
-# Created On: 2019-01-23 10:57:29 GMT+01:00
+# Created On: 2019-01-29 14:51:53 GMT+01:00
Address,Data
#
# Start configuration preamble
@@ -32,7 +32,7 @@ Address,Data
0x002D,0x04
0x002E,0x00
0x002F,0x00
-0x0030,0xB7
+0x0030,0x3B
0x0031,0x00
0x0032,0x00
0x0033,0x00
@@ -40,7 +40,7 @@ Address,Data
0x0035,0x00
0x0036,0x00
0x0037,0x00
-0x0038,0xB7
+0x0038,0x3B
0x0039,0x00
0x003A,0x00
0x003B,0x00
@@ -49,7 +49,7 @@ Address,Data
0x003F,0x22
0x0040,0x04
0x0041,0x00
-0x0042,0x0E
+0x0042,0x0D
0x0043,0x00
0x0044,0x00
0x0045,0x0C
@@ -77,9 +77,9 @@ Address,Data
0x005B,0x00
0x005C,0x00
0x005D,0x00
-0x005E,0xE3
-0x005F,0x38
-0x0060,0x2E
+0x005E,0x8D
+0x005F,0x8C
+0x0060,0x2D
0x0061,0x01
0x0062,0x00
0x0063,0x00
@@ -97,12 +97,12 @@ Address,Data
0x009A,0x02
0x009B,0x20
0x009D,0x00
-0x009E,0xA0
-0x00A0,0x80
+0x009E,0x40
+0x00A0,0x20
0x00A2,0x02
-0x00A8,0x4A
-0x00A9,0xEE
-0x00AA,0x15
+0x00A8,0x7F
+0x00A9,0xD8
+0x00AA,0x0F
0x00AB,0x00
0x00AC,0x00
0x0102,0x01
@@ -116,7 +116,7 @@ Address,Data
0x0110,0x00
0x0112,0x01
0x0113,0x09
-0x0114,0x3B
+0x0114,0x3D
0x0115,0x00
0x0117,0x02
0x0118,0x09
@@ -138,7 +138,7 @@ Address,Data
0x012C,0x09
0x012D,0x3B
0x012E,0x00
-0x0130,0x06
+0x0130,0x02
0x0131,0x09
0x0132,0x3D
0x0133,0x00
@@ -165,8 +165,8 @@ Address,Data
0x020F,0x00
0x0210,0x00
0x0211,0x00
-0x0212,0xA9
-0x0213,0x01
+0x0212,0x41
+0x0213,0x00
0x0214,0x00
0x0215,0x00
0x0216,0x00
@@ -202,26 +202,26 @@ Address,Data
0x0235,0x00
0x0236,0x00
0x0237,0x00
-0x0238,0x00
-0x0239,0x7F
+0x0238,0x69
+0x0239,0xD9
0x023A,0x00
0x023B,0x00
0x023C,0x00
-0x023D,0x00
-0x023E,0x80
-0x024A,0x01
+0x023D,0xF0
+0x023E,0xD2
+0x024A,0x03
0x024B,0x00
0x024C,0x00
-0x024D,0x01
+0x024D,0x03
0x024E,0x00
0x024F,0x00
0x0250,0x00
0x0251,0x00
0x0252,0x00
-0x0253,0x01
+0x0253,0x03
0x0254,0x00
0x0255,0x00
-0x0256,0x01
+0x0256,0x03
0x0257,0x00
0x0258,0x00
0x0259,0x00
@@ -233,25 +233,25 @@ Address,Data
0x025F,0x00
0x0260,0x00
0x0261,0x00
-0x0262,0x00
+0x0262,0x01
0x0263,0x00
0x0264,0x00
0x0268,0x00
0x0269,0x00
0x026A,0x00
-0x026B,0x4A
+0x026B,0x42
0x026C,0x49
-0x026D,0x54
-0x026E,0x32
-0x026F,0x5F
-0x0270,0x32
-0x0271,0x34
-0x0272,0x30
+0x026D,0x49
+0x026E,0x5F
+0x026F,0x46
+0x0270,0x50
+0x0271,0x47
+0x0272,0x41
0x0302,0x00
0x0303,0x00
0x0304,0x00
-0x0305,0x80
-0x0306,0x0D
+0x0305,0x00
+0x0306,0x07
0x0307,0x00
0x0308,0x00
0x0309,0x00
@@ -345,23 +345,23 @@ Address,Data
0x0362,0x00
0x0487,0x00
0x0508,0x14
-0x0509,0x21
-0x050A,0x0E
-0x050B,0x0D
-0x050C,0x03
+0x0509,0x22
+0x050A,0x0D
+0x050B,0x0C
+0x050C,0x01
0x050D,0x3F
-0x050E,0x19
-0x050F,0x2D
+0x050E,0x18
+0x050F,0x2C
0x0510,0x09
0x0511,0x08
-0x0512,0x03
+0x0512,0x01
0x0513,0x3F
0x0515,0x00
0x0516,0x00
0x0517,0x00
0x0518,0x00
-0x0519,0xEE
-0x051A,0x08
+0x0519,0xD8
+0x051A,0x02
0x051B,0x00
0x051C,0x00
0x051D,0x00
@@ -375,8 +375,8 @@ Address,Data
0x052E,0x19
0x052F,0x19
0x0531,0x00
-0x0532,0xDA
-0x0533,0x0A
+0x0532,0x54
+0x0533,0x03
0x0534,0x00
0x0535,0x00
0x0536,0x0C
diff --git a/Python/data/Si5345-2-BII_FTSW-Registers.txt b/Python/data/Si5345-2-BII_FTSW-Registers.txt
new file mode 100644
index 0000000000000000000000000000000000000000..de900b39a23167c934294817f3364dc631e78f64
--- /dev/null
+++ b/Python/data/Si5345-2-BII_FTSW-Registers.txt
@@ -0,0 +1,410 @@
+# Si538x/4x Registers Script
+#
+# Part: Si5345
+# Project File: D:\Work\Belle2 DAQ\pllsconfig\Si5345-2-BII_FTSW.slabtimeproj
+# Design ID: BII_FTSW
+# Includes Pre/Post Download Control Register Writes: Yes
+# Die Revision: A2
+# Creator: ClockBuilder Pro v2.29 [2018-11-04]
+# Created On: 2019-01-29 14:16:25 GMT+01:00
+Address,Data
+#
+# Start configuration preamble
+0x0B24,0xD8
+0x0B25,0x00
+0x0540,0x01
+# End configuration preamble
+#
+# Delay 300 msec
+# Delay is worst case time for device to complete any calibration
+# that is running due to device state change previous to this script
+# being processed.
+#
+# Start configuration registers
+0x000B,0x68
+0x0016,0x02
+0x0017,0x1C
+0x0018,0xEE
+0x0019,0xDD
+0x001A,0xDF
+0x002B,0x02
+0x002C,0x01
+0x002D,0x01
+0x002E,0x3B
+0x002F,0x00
+0x0030,0x00
+0x0031,0x00
+0x0032,0x00
+0x0033,0x00
+0x0034,0x00
+0x0035,0x00
+0x0036,0x3B
+0x0037,0x00
+0x0038,0x00
+0x0039,0x00
+0x003A,0x00
+0x003B,0x00
+0x003C,0x00
+0x003D,0x00
+0x003F,0x11
+0x0040,0x04
+0x0041,0x0D
+0x0042,0x00
+0x0043,0x00
+0x0044,0x00
+0x0045,0x0C
+0x0046,0x32
+0x0047,0x00
+0x0048,0x00
+0x0049,0x00
+0x004A,0x31
+0x004B,0x00
+0x004C,0x00
+0x004D,0x00
+0x004E,0x05
+0x004F,0x00
+0x0050,0x0F
+0x0051,0x03
+0x0052,0x00
+0x0053,0x00
+0x0054,0x00
+0x0055,0x02
+0x0056,0x00
+0x0057,0x00
+0x0058,0x00
+0x0059,0x03
+0x005A,0x8D
+0x005B,0x8C
+0x005C,0x2D
+0x005D,0x01
+0x005E,0x00
+0x005F,0x00
+0x0060,0x00
+0x0061,0x00
+0x0062,0x00
+0x0063,0x00
+0x0064,0x00
+0x0065,0x00
+0x0066,0x00
+0x0067,0x00
+0x0068,0x00
+0x0069,0x00
+0x0092,0x00
+0x0093,0x00
+0x0095,0x00
+0x0096,0x00
+0x0098,0x00
+0x009A,0x02
+0x009B,0x20
+0x009D,0x00
+0x009E,0x40
+0x00A0,0x20
+0x00A2,0x02
+0x00A8,0x7F
+0x00A9,0xD8
+0x00AA,0x0F
+0x00AB,0x00
+0x00AC,0x00
+0x0102,0x01
+0x0108,0x02
+0x0109,0x09
+0x010A,0x3D
+0x010B,0x00
+0x010D,0x02
+0x010E,0x09
+0x010F,0x3D
+0x0110,0x00
+0x0112,0x01
+0x0113,0x09
+0x0114,0x3D
+0x0115,0x00
+0x0117,0x02
+0x0118,0x09
+0x0119,0x3D
+0x011A,0x00
+0x011C,0x02
+0x011D,0x09
+0x011E,0x3D
+0x011F,0x00
+0x0121,0x01
+0x0122,0x09
+0x0123,0x3B
+0x0124,0x00
+0x0126,0x01
+0x0127,0x09
+0x0128,0x3B
+0x0129,0x00
+0x012B,0x01
+0x012C,0x09
+0x012D,0x3B
+0x012E,0x00
+0x0130,0x02
+0x0131,0x09
+0x0132,0x3D
+0x0133,0x00
+0x013A,0x01
+0x013B,0x09
+0x013C,0x3B
+0x013D,0x00
+0x013F,0x00
+0x0140,0x00
+0x0141,0x40
+0x0142,0xFF
+0x0202,0x00
+0x0203,0x00
+0x0204,0x00
+0x0205,0x00
+0x0206,0x00
+0x0208,0x41
+0x0209,0x00
+0x020A,0x00
+0x020B,0x00
+0x020C,0x00
+0x020D,0x00
+0x020E,0x01
+0x020F,0x00
+0x0210,0x00
+0x0211,0x00
+0x0212,0x00
+0x0213,0x00
+0x0214,0x00
+0x0215,0x00
+0x0216,0x00
+0x0217,0x00
+0x0218,0x00
+0x0219,0x00
+0x021A,0x00
+0x021B,0x00
+0x021C,0x00
+0x021D,0x00
+0x021E,0x00
+0x021F,0x00
+0x0220,0x00
+0x0221,0x00
+0x0222,0x00
+0x0223,0x00
+0x0224,0x00
+0x0225,0x00
+0x0226,0x00
+0x0227,0x00
+0x0228,0x00
+0x0229,0x00
+0x022A,0x00
+0x022B,0x00
+0x022C,0x00
+0x022D,0x00
+0x022E,0x00
+0x022F,0x00
+0x0231,0x01
+0x0232,0x01
+0x0233,0x01
+0x0234,0x01
+0x0235,0x00
+0x0236,0x00
+0x0237,0x00
+0x0238,0x69
+0x0239,0xD9
+0x023A,0x00
+0x023B,0x00
+0x023C,0x00
+0x023D,0xF0
+0x023E,0xD2
+0x024A,0x03
+0x024B,0x00
+0x024C,0x00
+0x024D,0x03
+0x024E,0x00
+0x024F,0x00
+0x0250,0x00
+0x0251,0x00
+0x0252,0x00
+0x0253,0x03
+0x0254,0x00
+0x0255,0x00
+0x0256,0x03
+0x0257,0x00
+0x0258,0x00
+0x0259,0x00
+0x025A,0x00
+0x025B,0x00
+0x025C,0x00
+0x025D,0x00
+0x025E,0x00
+0x025F,0x00
+0x0260,0x00
+0x0261,0x00
+0x0262,0x01
+0x0263,0x00
+0x0264,0x00
+0x0268,0x00
+0x0269,0x00
+0x026A,0x00
+0x026B,0x42
+0x026C,0x49
+0x026D,0x49
+0x026E,0x5F
+0x026F,0x46
+0x0270,0x54
+0x0271,0x53
+0x0272,0x57
+0x0302,0x00
+0x0303,0x00
+0x0304,0x00
+0x0305,0x00
+0x0306,0x07
+0x0307,0x00
+0x0308,0x00
+0x0309,0x00
+0x030A,0x00
+0x030B,0x80
+0x030C,0x00
+0x030D,0x00
+0x030E,0x00
+0x030F,0x00
+0x0310,0x00
+0x0311,0x00
+0x0312,0x00
+0x0313,0x00
+0x0314,0x00
+0x0315,0x00
+0x0316,0x00
+0x0317,0x00
+0x0318,0x00
+0x0319,0x00
+0x031A,0x00
+0x031B,0x00
+0x031C,0x00
+0x031D,0x00
+0x031E,0x00
+0x031F,0x00
+0x0320,0x00
+0x0321,0x00
+0x0322,0x00
+0x0323,0x00
+0x0324,0x00
+0x0325,0x00
+0x0326,0x00
+0x0327,0x00
+0x0328,0x00
+0x0329,0x00
+0x032A,0x00
+0x032B,0x00
+0x032C,0x00
+0x032D,0x00
+0x032E,0x00
+0x032F,0x00
+0x0330,0x00
+0x0331,0x00
+0x0332,0x00
+0x0333,0x00
+0x0334,0x00
+0x0335,0x00
+0x0336,0x00
+0x0337,0x00
+0x0338,0x00
+0x0339,0x1F
+0x033B,0x00
+0x033C,0x00
+0x033D,0x00
+0x033E,0x00
+0x033F,0x00
+0x0340,0x00
+0x0341,0x00
+0x0342,0x00
+0x0343,0x00
+0x0344,0x00
+0x0345,0x00
+0x0346,0x00
+0x0347,0x00
+0x0348,0x00
+0x0349,0x00
+0x034A,0x00
+0x034B,0x00
+0x034C,0x00
+0x034D,0x00
+0x034E,0x00
+0x034F,0x00
+0x0350,0x00
+0x0351,0x00
+0x0352,0x00
+0x0353,0x00
+0x0354,0x00
+0x0355,0x00
+0x0356,0x00
+0x0357,0x00
+0x0358,0x00
+0x0359,0x00
+0x035A,0x00
+0x035B,0x00
+0x035C,0x00
+0x035D,0x00
+0x035E,0x00
+0x035F,0x00
+0x0360,0x00
+0x0361,0x00
+0x0362,0x00
+0x0487,0x00
+0x0508,0x14
+0x0509,0x22
+0x050A,0x0D
+0x050B,0x0C
+0x050C,0x01
+0x050D,0x3F
+0x050E,0x18
+0x050F,0x2C
+0x0510,0x09
+0x0511,0x08
+0x0512,0x01
+0x0513,0x3F
+0x0515,0x00
+0x0516,0x00
+0x0517,0x00
+0x0518,0x00
+0x0519,0xD8
+0x051A,0x02
+0x051B,0x00
+0x051C,0x00
+0x051D,0x00
+0x051E,0x00
+0x051F,0x80
+0x0521,0x21
+0x052A,0x01
+0x052B,0x01
+0x052C,0x0F
+0x052D,0x03
+0x052E,0x19
+0x052F,0x19
+0x0531,0x00
+0x0532,0x54
+0x0533,0x03
+0x0534,0x00
+0x0535,0x00
+0x0536,0x0C
+0x0537,0x00
+0x0538,0x00
+0x0539,0x00
+0x0802,0x35
+0x0803,0x05
+0x0804,0x00
+0x090E,0x02
+0x0943,0x00
+0x0949,0x01
+0x094A,0x01
+0x0A02,0x00
+0x0A03,0x01
+0x0A04,0x01
+0x0A05,0x01
+0x0B44,0x2F
+0x0B46,0x00
+0x0B47,0x0E
+0x0B48,0x0E
+0x0B4A,0x1E
+# End configuration registers
+#
+# Start configuration postamble
+0x0514,0x01
+0x001C,0x01
+0x0540,0x00
+0x0B24,0xDB
+0x0B25,0x02
+# End configuration postamble
diff --git a/Python/lli/i2c.py b/Python/lli/i2c.py
index 5ae2aab613b7707edb8263cabb4e97ef5870e50c..a21e9522b5b75cee2ca723ece694c236b78b01f5 100644
--- a/Python/lli/i2c.py
+++ b/Python/lli/i2c.py
@@ -46,7 +46,7 @@ initDone = [[False for x in xrange(NB_OF_BUSES)] for x in xrange(NB_OF_BOARDS)]
def init(dev,bus):
- print("init i2c on dev {} bus {}".format(dev, bus))
+ #print("init i2c on dev {} bus {}".format(dev, bus))
lli.i2c_init(dev,bus, 100000000, 100000)
#lli.i2c_init(bus, 125000000, 100000)
initDone[dev][bus] = True
diff --git a/Scripts/pll_status.py b/Scripts/pll_status.py
index a4cfce5aa98714b4b71fcd3b05a59aeabbb12685..245938249eb4ce693b2f31d80bdd5e70ba1e94be 100755
--- a/Scripts/pll_status.py
+++ b/Scripts/pll_status.py
@@ -1,13 +1,10 @@
#!/usr/bin/python
-# -*- coding: utf8 -*-
"""
- xcvr_status.py -- module to display pll status
+ pll_status.py -- module to display pll status
Author
JPC : 02/10/2018
-
-
-
+ Eric Jules: 01/12/2018, adapt for Belle II
"""
import time
import os
@@ -104,7 +101,7 @@ def pll_window(pll, device, fpga, freq, conf, win):
def fanout_window(fpga, win):
status, frequency_read = fpga.read_pll_port_frequency("SI5340", 0)
- win.addstr(2, 1, "Oscillator or face plate clock : ",curses.A_BOLD)
+ win.addstr(2, 1, "Face plate clock : ",curses.A_BOLD)
if frequency_read < 127000000 or frequency_read > 128000000:
win.addstr(str(frequency_read/1000)+" kHz", RED)
win.addstr(" Warning : frequency out of range", YELLOW)
@@ -176,48 +173,29 @@ def draw_menu(stdscr, dev):
2: "SI5345_U48",
3: "SI5344_U54"
}
+ ### Files for configuration for FTSW clock
files1b = \
- {1: "../data/Si5345-RevB-JIT1_40_jitter1_input0_40MHz-Registers.txt",
- 2: "../data/Si5345-RevB-JIT2_40_jitter2_input0_40MHz-Registers.txt",
- 3: "../data/Si5344-RevB-TFC_40-Registers.txt"
- }
- files1d = \
- {1: "../data/Si5345-RevD-JIT1_40_jitter1_input0_40MHz-Registers.txt",
- 2: "../data/Si5345-RevD-JIT2_40_jitter2_input0_40MHz-Registers.txt",
- 3: "../data/Si5344-RevD-TFC_40-Registers.txt"
+ {1: "../data/Si5345-1-BII_FTSW-Registers.txt",
+ 2: "../data/Si5345-2-BII_FTSW-Registers.txt",
+ 3: "../data/Si5344-BII_FTSW-Registers.txt"
}
conf1 = \
- {1: ["Expected frequency = 40.0789 MHz", "Not used", "Not used", "Not used"],
- 2: ["Expected frequency = 40.0789 MHz", "Not used", "Not used", "Not used"],
- 3: ["Expected frequency = 40.0789 MHz", "Not used", "Not used", "Not used"]
+ {1: ["Expected frequency = 127.216 MHz", "Not used", "Not used", "Not used"],
+ 2: ["Expected frequency = 127.216 MHz", "Not used", "Not used", "Not used"],
+ 3: ["Expected frequency = 127.216 MHz", "Not used", "Not used", "Not used"]
}
# Modif EJ EP 17-01-2019 changement 2 premiers fichiers programmation pll
- #files2b = \
- #{1: "../data/Si5345-RevB-JIT1_250_jitter1_input1_250MHz-Registers.txt",
- #2: "../data/Si5345-RevB-JIT2_250_jitter2_input1_250MHz-Registers.txt",
- #3: "../data/Si5344-RevB-TFC_127-Registers.txt"
- #}
+ ### Files for configuration for oscillator clock
files2b = \
- {1: "../data/Si5345-RevB-JIT1_255-JIT1_240_jitter1_input1_255MHz_new-Registers.txt",
- 2: "../data/Si5345-RevB-JIT2_255-JIT2_240_jitter2_input1_255MHz_new-Registers.txt",
- 3: "../data/Si5344-RevB-TFC_127-Registers.txt"
- }
-
- files2d = \
- {1: "../data/Si5345-RevD-JIT1_240_jitter1_input1_240MHz-Registers.txt",
- 2: "../data/Si5345-RevD-JIT2_240_jitter2_input1_240MHz-Registers.txt",
- 3: "../data/Si5344-RevD-TFC_40-Registers.txt"
+ {1: "../data/Si5345-1-BII_FPGA-Registers.txt",
+ 2: "../data/Si5345-2-BII_FPGA-Registers.txt",
+ 3: "../data/Si5344-BII_OSCI-Registers.txt"
}
# Modif EJ EP 17-01-2019 changement 2 premiers fichiers programmation pll
- #conf2 = \
- #{1: ["Not used", "Expected frequency = 250 MHz", "Not used", "Not used"],
- #2: ["Not used", "Expected frequency = 250 MHz", "Not used", "Not used"],
- #3: ["Expected frequency = 127 MHz", "Not used", "Not used", "Not used"]
- #}
conf2 = \
{1: ["Not used", "Expected frequency = 127.216 MHz", "Not used", "Not used"],
2: ["Not used", "Expected frequency = 127.216 MHz", "Not used", "Not used"],
- 3: ["Expected frequency = 127 MHz", "Not used", "Not used", "Not used"]
+ 3: ["Expected frequency = 127.216 MHz", "Not used", "Not used", "Not used"]
}
freq = \
{1: {
@@ -314,7 +292,7 @@ def draw_menu(stdscr, dev):
y_max - 9,
0)
win5.box()
- win5.addstr(1, 1, "Clock Fanout", CYAN | curses.A_BOLD)
+ win5.addstr(1, 1, "Clock FTSW", CYAN | curses.A_BOLD)
win5.refresh()
win6 = stdscr.subwin(4,
@@ -322,7 +300,7 @@ def draw_menu(stdscr, dev):
y_max - 4,
0)
win6.box()
- win6.addstr(1, 1, "F2: Program PLLs (source = fanout), F3: Program PLLs (source = FPGA))", CYAN | curses.A_BOLD)
+ win6.addstr(1, 1, "F2: Program PLLs (source = FTSW), F3: Program PLLs (source = Osci.)", CYAN | curses.A_BOLD)
win6.addstr(2, 1, "F4: Clear LOS/OOF/LOL Flag, F5 : Hard reset, F6: Soft reset", CYAN | curses.A_BOLD)
win6.refresh()
@@ -347,7 +325,7 @@ def draw_menu(stdscr, dev):
win1.move(2, 1)
win1.clrtobot()
win1.box()
- win1.addstr(3, 1, "Programming PLLs (source = fanout)")
+ win1.addstr(3, 1, "Programming PLLs (source = FTSW)")
files = files1b
conf = conf1
program_plls(plls, devices, files, win1)
@@ -364,7 +342,7 @@ def draw_menu(stdscr, dev):
win1.move(2, 1)
win1.clrtobot()
win1.box()
- win1.addstr(3, 1, "Programming PLLs (source = FPGA) ")
+ win1.addstr(3, 1, "Programming PLLs (source = Oscillator) ")
files = files2b
conf = conf2
program_plls(plls, devices, files, win1)