diff --git a/Pcie40Applications/regconfig.cpp b/Pcie40Applications/regconfig.cpp index 4c821dc698965918816f4f5cccfab396c482fc9f..9a2295d892765312f0b14f91d6c9b4a7a1af9d3d 100644 --- a/Pcie40Applications/regconfig.cpp +++ b/Pcie40Applications/regconfig.cpp @@ -348,6 +348,7 @@ int main(int argc, char** argv){ pcie40reg_t pcie40; int result = -1; +<<<<<<< HEAD if(PCIE40_REG && READ_ONLY){ result = ecs_read( dev_slot , SLC_BAR , addr); printf("reg%08x = %08x\n", addr, result); @@ -391,6 +392,46 @@ int main(int argc, char** argv){ }else{ printf("ERROR: b2link-%02d is down or not ready\n", ch); } +======= + if(pcie40_b2l_status(dev_slot, ch) && pcie40_b2l_rxready(dev_slot, ch) && pcie40_b2l_txready(dev_slot, ch)){ + if(USE_FEE8 && READ_ONLY){ + result = pcie40_readfee8( dev_slot , ch , addr ); + printf("reg%04x = %08x\n", addr, result); + }else if(USE_FEE8 && WRITE){ + result = pcie40_writefee8( dev_slot , ch , addr, data ); + if(result == 0) + printf("Write 0x%04x to register 0x%04x\n", data, addr); + else + printf("ERROR: Failed to write 0x%04x to register 0x%04x\n", data, addr); + }else if(USE_FEE32 && READ_ONLY){ + result = pcie40_readfee32( dev_slot , ch , addr ); + printf("reg%04x = %08x\n", addr, result); + }else if(USE_FEE32 && WRITE){ + result = pcie40_writefee32( dev_slot , ch , addr, data ); + if(result == 0) + printf("Write 0x%08x to register 0x%04x\n", data, addr); + else + printf("ERROR: Failed to write 0x%08x to register %04x\n", data, addr); + }else if(STREAM){ + if(STREAM_ARICH) + result = pcie40_writestream_arich( dev_slot , ch , filename ) ; + else + result = pcie40_writestream_klm( dev_slot , ch , filename ) ; + if(result == 0) + std::cerr<<"Succeed streaming file: " << filename << std::endl; + else + std::cerr<<"ERROR: Failed streaming file: " << filename << std::endl; + } + + //This is only frame for register operation in the furture + if(OP_FLAG){ + unsigned int op_addr = hsreg( operation ); + pcie40_op(dev_slot, ch, op_addr, addr, data); + } + }else{ + printf("ERROR: b2link-%02d is down or not ready\n", ch); + } +>>>>>>> 8159e3177249eb1433db0b01707bd77ba8b09f0d // close pcie40 device driver for current process ecs_close( dev_slot , SLC_BAR) ;