From 5681d374267cd613846b6e8b41dd2e65e96439a4 Mon Sep 17 00:00:00 2001
From: Patrick Robbe <robbe@lal.in2p3.fr>
Date: Tue, 11 Jun 2019 18:48:30 +0900
Subject: [PATCH] Remove old files
---
Pcie40DriverLibraries/Makefile | 28 ++++++++
Pcie40DriverLibraries/ecs_driverlib.c | 94 +++++++++++++++++++++++++++
Pcie40DriverLibraries/ecs_driverlib.h | 44 +++++++++++++
Pcie40DriverLibraries/flags.mk | 3 +
4 files changed, 169 insertions(+)
create mode 100644 Pcie40DriverLibraries/Makefile
create mode 100644 Pcie40DriverLibraries/ecs_driverlib.c
create mode 100644 Pcie40DriverLibraries/ecs_driverlib.h
create mode 100755 Pcie40DriverLibraries/flags.mk
diff --git a/Pcie40DriverLibraries/Makefile b/Pcie40DriverLibraries/Makefile
new file mode 100644
index 0000000..aa2d399
--- /dev/null
+++ b/Pcie40DriverLibraries/Makefile
@@ -0,0 +1,28 @@
+HERE :=$(strip $(realpath $(dir $(lastword $(MAKEFILE_LIST)))))
+TOP :=$(realpath $(HERE))
+
+include $(TOP)/flags.mk
+
+LIBPCIE40_ECS.A :=libpcie40driver_ecs.a
+LIBPCIE40_ECS.A_OBJS =pcie40_driverlib.o ecs_driverlib.o
+LIBPCIE40_ECS.A_CFLAGS =$(CFLAGS) -I$(TOP) -I$(TOP)/../Pcie40Driver
+LIBPCIE40_ECS.A_ARFLAGS =rcs
+LIBPCIE40_ECS.A_INSTALL =$(PREFIX)/lib$(LIBDIR_SUFFIX)
+
+LIBPCIE40_ECS.SO :=libpcie40driver_ecs.so
+LIBPCIE40_ECS.SO_OBJS =$(LIBPCIE40_ECS.A_OBJS:.o=.pic.o)
+LIBPCIE40_ECS.SO_CFLAGS =$(LIBPCIE40_ECS.A_CFLAGS)
+LIBPCIE40_ECS.SO_LDFLAGS =-shared
+LIBPCIE40_ECS.SO_INSTALL =$(LIBPCIE40_ECS.A_INSTALL)
+
+LIBPCIE40_ECS_HDRS :=ecs.h
+LIBPCIE40_ECS_HDRS_INSTALL =$(PREFIX)/include/pcie40
+
+VPATH :=$(TOP)
+
+include $(TOP)/rules.mk
+ifeq ($(ENABLE_PCIE40), true)
+$(eval $(call ODIR_template,LIBPCIE40_ECS.A))
+$(eval $(call ODIR_template,LIBPCIE40_ECS.SO))
+endif
+$(eval $(call DEFAULT_template))
diff --git a/Pcie40DriverLibraries/ecs_driverlib.c b/Pcie40DriverLibraries/ecs_driverlib.c
new file mode 100644
index 0000000..0dfec0f
--- /dev/null
+++ b/Pcie40DriverLibraries/ecs_driverlib.c
@@ -0,0 +1,94 @@
+#include <stdio.h>
+#include <unistd.h>
+#include <string.h>
+#include <errno.h>
+
+#include <sys/types.h>
+#include <sys/stat.h>
+#include <fcntl.h>
+
+#include <linux/ioctl.h>
+#include <sys/ioctl.h>
+#include <sys/mman.h>
+
+#include "ecs_driverlib.h"
+#include "pcie40_driverlib.h"
+#include "pcie40_ioctl.h"
+
+//`p40_ecs_open`
+int p40_ecs_open(int dev, int bar, uint32_t **regs)
+{
+ int fd;
+ char devname[32];
+
+ char *suffix;
+ switch (bar) {
+ case 0:
+ suffix = "bar0";
+ break;
+ case 2:
+ suffix = "bar2";
+ break;
+ default:
+ return -EINVAL;
+ }
+
+ if (p40_get_devname(dev, suffix, devname, sizeof(devname)) < 0) {
+ perror("p40_get_devname()");
+ return -1;
+ }
+
+ if ((fd = open(devname, O_RDWR)) == -1){
+ perror("open()");
+ return -1;
+ }
+
+ int bar_size = p40_ecs_bar_size(fd);
+ if (bar_size < 0) {
+ close(fd);
+ return -1;
+ }
+
+ *regs = mmap(NULL, bar_size, PROT_READ | PROT_WRITE, MAP_SHARED, fd, 0);
+ if (*regs == NULL) {
+ perror("mmap()");
+ close(fd);
+ return -1;
+ }
+
+ return fd;
+}
+
+//`p40_ecs_close`
+void p40_ecs_close(int fd, uint32_t *regs)
+{
+ int bar_size = p40_ecs_bar_size(fd);
+ munmap(regs, bar_size);
+ close(fd);
+}
+
+//`p40_ecs_bar_size`
+int p40_ecs_bar_size(int fd)
+{
+ int ret;
+
+ //? See ioctl.pcie`P40_ECS_GET_BAR_SIZE` .
+ ret = ioctl(fd, P40_ECS_GET_BAR_SIZE);
+ if (ret < 0) {
+ perror("ioctl(P40_ECS_GET_BAR_SIZE)");
+ return -1;
+ }
+ return ret;
+}
+
+//`p40_ecs_w32`
+void p40_ecs_w32(uint32_t volatile *regs, uint32_t addr, uint32_t val)
+{
+ regs[addr >> 2] = val;
+}
+
+//`p40_ecs_r32`
+uint32_t p40_ecs_r32(uint32_t volatile *regs, uint32_t addr)
+{
+ return regs[addr >> 2];
+}
diff --git a/Pcie40DriverLibraries/ecs_driverlib.h b/Pcie40DriverLibraries/ecs_driverlib.h
new file mode 100644
index 0000000..4227e6b
--- /dev/null
+++ b/Pcie40DriverLibraries/ecs_driverlib.h
@@ -0,0 +1,44 @@
+#ifndef __PCIE40_ECS_H
+#define __PCIE40_ECS_H
+
+#include <stdint.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+//dg`wt.pcie40.c.ecs` In order to interact with the ECS interface of the PCIe40 driver, C libraries are provided (*libpcie40_ecs.so* and *libpcie40_ecs.a*).
+// To use these libraries, add ``#include <lhcb/pcie40/ecs.h>`` to your source code and ``-lpcie40_ecs`` to your linker flags.
+// This API is very simple, consisting only of a handful of functions to create I/O memory mappings and to access individual I/O registers, see <<PCIe40 driver ECS API>>.
+
+//`p40_ecs_open` Create file descriptor to access an ECS BAR.
+int p40_ecs_open(int dev, int bar, uint32_t **regs);//?>
+//>`dev` Device identifier corresponding to the given board.
+//>`bar` PCI BAR to access, valid values are 0 (for the user registers) and 2 (for the low-level registers).
+//<`regs` Address of a valid +uint32_t *+ pointer. It is set by the function upon return.
+
+//`p40_ecs_close` Destroy file descriptor to an open ECS BAR.
+void p40_ecs_close(int fd, uint32_t *regs);//?>
+//>`fd` File descriptor returned by `p40_ecs_open` .
+//>`regs` Pointer populated by `p40_ecs_open` .
+
+//`p40_ecs_bar_size` Query driver for size of a given PCI BAR.
+int p40_ecs_bar_size(int fd);//?>
+//>`fd` File descriptor returned by `p40_ecs_open` .
+
+//`p40_ecs_w32` Write register at given address.
+void p40_ecs_w32(uint32_t volatile *regs, uint32_t addr, uint32_t val);//?>
+//>`regs` Pointer populated by `p40_ecs_open` .
+//>`addr` Address of register.
+//>`val` 32-bit value to write.
+
+//`p40_ecs_r32` Read register at given address.
+uint32_t p40_ecs_r32(uint32_t volatile *regs, uint32_t addr);//?>
+//>`regs` Pointer populated by `p40_ecs_open` .
+//>`addr` Address of register.
+
+#ifdef __cplusplus
+} //extern "C"
+#endif
+
+#endif//__PCIE40_ECS_H
diff --git a/Pcie40DriverLibraries/flags.mk b/Pcie40DriverLibraries/flags.mk
new file mode 100755
index 0000000..fe8e02c
--- /dev/null
+++ b/Pcie40DriverLibraries/flags.mk
@@ -0,0 +1,3 @@
+export ENABLE_PCIE40 ?=true
+
+export PREFIX ?=/usr
--
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