diff --git a/README.md b/README.md index 8ee415058445c1b09ac7393db05e9d049f0929cd..3572cd04e271347c3252664eb4005b77c3936299 100644 --- a/README.md +++ b/README.md @@ -1,38 +1,57 @@ # Software -Instructions how to install the software +## Instructions how to install the software `sudo yum install kernel-devel` + `sudo yum install epel-release` + `sudo yum install python-pip` + `sudo yum install python-devel` + `sudo yum groupinstall 'development tools'` + `pip install py` To clone the repository using ```ssh://git@stash.desy.de:7999/bidu/software.git``` Build the software (driver, interface libraries, application programs ...) + `cd Software` + `make` -To use the software +##To use the software + +- Setup the environment variables --Setup the environment variables `cd Scripts` + `source setup.sh` --Re-load the PCIe bus (mandatory after a new firmware is programmed) + +- Re-load the PCIe bus (mandatory after a new firmware is programmed) + `pcie40_reload` --Sometimes, reloading the driver is also mandatory (after power off or when something goes wrong) - -How to use the application programs. --`python pll_status.py 0`: configure the clock tree. Press `F2` to use the clock from FTSW or `F3` to use the local oscillator clock (also with a frequency of 127.1 MHz). This application needs a large terminal to work correctly otherwise it will not open --`python pll_status_small.py 0`: configure the clock tree. Press `F2` to use the clock from FTSW or `F3` to use the local oscillator clock (also with a frequency of 127.1 MHz). This application works on small terminal window but will display less information than `pll_status.py` --`python testBL.py`: send a trigger from the FTSW board and read data back in the PCIe40 (edit the file to adapt the name of the VME controller board to communicate with the FTSW module) --`pcie40_reload`: reload the driver after programming the firmware of the PCIe40 board. After reloading the driver, you also need to correct the device file permissions with `sudo chmod o+rw /dev/pcie40_0_*` --`pcie40_program -c 1 file.sof`: program the firmware of the PCIe40 board with `file.sof` --`pcie40_ecs -b 2 -a N -r`: read 32 bits at address N of the BAR2 register space --`pcie40_ecs -b 2 -a N -w D`: write D at address N of the BAR register space --`pcie40_b2slc`: slow control register access - -Start-Kit manual for usage of PCIe40 can be found [here](https://confluence.desy.de/display/BI/PCIe40+Documentation?preview=/145594091/145594869/PCIe40_StartKit.pdf) + +- Sometimes, reloading the driver is also mandatory (after power off or when something goes wrong) + +## How to use the application programs. +- `python pll_status.py 0`: configure the clock tree. Press `F2` to use the clock from FTSW or `F3` to use the local oscillator clock (also with a frequency of 127.1 MHz). This application needs a large terminal to work correctly otherwise it will not open + +- `python pll_status_small.py 0`: configure the clock tree. Press `F2` to use the clock from FTSW or `F3` to use the local oscillator clock (also with a frequency of 127.1 MHz). This application works on small terminal window but will display less information than `pll_status.py` + +- `python testBL.py`: send a trigger from the FTSW board and read data back in the PCIe40 (edit the file to adapt the name of the VME controller board to communicate with the FTSW module) + +- `pcie40_reload`: reload the driver after programming the firmware of the PCIe40 board. After reloading the driver, you also need to correct the device file permissions with `sudo chmod o+rw /dev/pcie40_0_*` + +- `pcie40_program -c 1 file.sof`: program the firmware of the PCIe40 board with `file.sof` + +- `pcie40_ecs -b 2 -a N -r`: read 32 bits at address N of the BAR2 register space + +- `pcie40_ecs -b 2 -a N -w D`: write D at address N of the BAR register space + +- `pcie40_b2slc`: slow control register access + +## Start-Kit manual for usage of PCIe40 can be found [here](https://confluence.desy.de/display/BI/PCIe40+Documentation?preview=/145594091/145594869/PCIe40_StartKit.pdf)